AR# 50719


Clocking Wizard v3.6/v4.2 - Release Notes and Known Issues


This Release Note is for the Clocking Wizard v3.6 released in ISE Design Suite14.2 and v4.2 released in Vivado 2012.2 tools which contains the following:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues


General Information

The Clocking Wizard v3.6 and v4.2 supports the 7 series FPGAs and Zynq devices.

New Features in v3.6

Support for Spread Spectrum clocking in 7 series FPGAs added in v3.6.

New Features in v4.2

Support for Spread Spectrum clocking in 7 series FPGAs added in v4.2. Also, the Fast Simulation feature was added.

Bug Fixes in v3.6 & v4.2

No bug fixes.

Known Issues in v3.6

In v3.6 when targeting a Virtex-6 the MMCM_ADV module is missing for a VHDL project. To work around this issue, use the Clocking Wizard v3.5 for Virtex-6 VHDL projects.

In v3.6 of the Clocking Wizard, if you select a BUFHCE as the output buffer, the example design might be unroutable with the default constraints. The BUFHCE can drive a single clock region.

In the Clocking Wizard v3.5, example design implementation with the BUFHCE as the output buffer might fail due to the placement of logic in multiple clock regions. To work around the issue, you can provide constraints to lock the output clock pin and the BUFHCE into the same bank.

Known Issues in v4.2

1. On the Output Clock Settings page, you can choose what the clock output drives (e.g., BUFG or BUFH). However, due to a Wizard issue it does not allow you to independently select different drives for the individual outputs. To work around this issue, instantiate the <core_name>.vhd (rather than the .xci) and change the buffer instantiation.

2. If simulating the VHDL example design, the following error might occur:

# ERROR: Freq of CLK_OUT[1] is not correct

This is due to a rounding issue in the frequency calculation for VHDL Unisim model; however, you can avoid this by using the Verilog model.

3. For VHDL project, if Spread Spectrum is enabled, there is a semicolon missing from the example design COUNT port declaration. This causes synthesis and simulation failure. The workaround is to add a semicolon in the example design and testbench for the COUNT port declaration as follows:

; : out std_logic;
AR# 50719
Date 07/31/2012
Status Archive
Type General Article
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