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AR# 50734

MIG 7 Series DDR3 - Additional levels of logic can cause certain configurations to fail timing

Description

Version Found: v1.6
Version Resolved and other Known Issues: See (Xilinx Answer 45195).


Certain memory configurations can fail timingif additional levels of logic are added within the controller path.

Solution

If timing failures occur within the controller logic of the MIG design, then the bank_state.v moduleshould be modified in the following way:

Original Code

// register output data pre-fifo almost full condition and fold in WR status

reg ofs_wr_rdy = 1'b0;

always @(posedge clk)

if(rst)

ofs_wr_rdy <= #TCQ 1'b0;

else

ofs_wr_rdy <= #TCQ ~(phy_mc_data_full && ~rd_wr_r);

wire ofs_rdy =

~phy_mc_cmd_full && ~phy_mc_ctl_full && ofs_wr_rdy;

// Disable priority feature for one state after a config to insure

// forward progress on the just installed io config.

reg override_demand_r;

wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;

always @(posedge clk) override_demand_r <= override_demand_ns;

output wire rts_col;

assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&

col_cmd_rts && ofs_rdy;

Modified Code

// Register ctl_full and cmd_full

reg phy_mc_ctl_full_r = 1'b0;

reg phy_mc_cmd_full_r = 1'b0;

always @(posedge clk)

if(rst) begin

phy_mc_ctl_full_r <= #TCQ 1'b0;

phy_mc_cmd_full_r <= #TCQ 1'b0;

end else begin

phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;

phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;

end

// register output data pre-fifo almost full condition and fold in WR status

reg ofs_rdy_r = 1'b0;

always @(posedge clk)

if(rst)

ofs_rdy_r <= #TCQ 1'b0;

else

ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);

// Disable priority feature for one state after a config to insure

// forward progress on the just installed io config.

reg override_demand_r;

wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;

always @(posedge clk) override_demand_r <= override_demand_ns;

output wire rts_col

assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&

col_cmd_rts && ofs_rdy_r;

Revision History
07/25/2012 - Initial release

AR# 50734
Date Created 07/11/2012
Last Updated 01/16/2013
Status Active
Type Known Issues
Devices
  • Kintex-7
IP
  • MIG 7 Series