Slack (setup path): -0.728ns (requirement - (data path - clock path skew + uncertainty))
Source: u_mig_7series_v1_4/c5_u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_phy_read_top/nd_io_inst[2].u_qdr_rld_phy_read_data_align/rd_ptr_0 (FF)
Destination:u_mig_7series_v1_4/c5_u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_phy_read_top/u_qdr_rld_phy_read_stage2_cal/mem_latency_31 (FF)
Requirement: 4.000ns
Data Path Delay:4.507ns (Levels of Logic = 5)
This is a result of a combinatorial path within the read data alignment logic that has a high number of fan-outs and route delays.
To work around the timing failure, the qdr_rld_phy_read_data_align.v module must have the following lines replaced:
Lines 103-108
reg [BYTE_LANE_WIDTH-1:0] memory_rd0 [15:0];
reg [BYTE_LANE_WIDTH-1:0] memory_fd0 [15:0];
reg [BYTE_LANE_WIDTH-1:0] memory_rd1 [15:0];
reg [BYTE_LANE_WIDTH-1:0] memory_fd1 [15:0];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
replaced with:
reg [BYTE_LANE_WIDTH/2-1:0] memory_rd0_0 [15:0];
reg [(BYTE_LANE_WIDTH+1)/2-1:0] memory_rd0_1 [15:0];
reg [BYTE_LANE_WIDTH/2-1:0] memory_fd0_0 [15:0];
reg [(BYTE_LANE_WIDTH+1)/2-1:0] memory_fd0_1 [15:0];
reg [BYTE_LANE_WIDTH/2-1:0] memory_rd1_0 [15:0];
reg [(BYTE_LANE_WIDTH+1)/2-1:0] memory_rd1_1 [15:0];
reg [BYTE_LANE_WIDTH/2-1:0] memory_fd1_0 [15:0];
reg [(BYTE_LANE_WIDTH+1)/2-1:0] memory_fd1_1 [15:0];
reg [3:0] wr_ptr /* synthesis syn_maxfan = (BYTE_LANE_WIDTH+1)/2 */;
reg [3:0] rd_ptr /* synthesis syn_maxfan = (BYTE_LANE_WIDTH+1)/2 */;
and Lines 141-150
memory_rd0[wr_ptr] <= iserdes_rd0;
memory_fd0[wr_ptr] <= iserdes_fd0;
memory_rd1[wr_ptr] <= iserdes_rd1;
memory_fd1[wr_ptr] <= iserdes_fd1;
end
assign rise_data0 = memory_rd0[rd_ptr];
assign fall_data0 = memory_fd0[rd_ptr];
assign rise_data1 = memory_rd1[rd_ptr];
assign fall_data1 = memory_fd1[rd_ptr];
replaced with
memory_rd0_0[wr_ptr] <= iserdes_rd0[BYTE_LANE_WIDTH/2-1:0];
memory_rd0_1[wr_ptr] <= iserdes_rd0[BYTE_LANE_WIDTH-1:BYTE_LANE_WIDTH/2];
memory_fd0_0[wr_ptr] <= iserdes_fd0[BYTE_LANE_WIDTH/2-1:0];
memory_fd0_1[wr_ptr] <= iserdes_fd0[BYTE_LANE_WIDTH-1:BYTE_LANE_WIDTH/2];
memory_rd1_0[wr_ptr] <= iserdes_rd1[BYTE_LANE_WIDTH/2-1:0];
memory_rd1_1[wr_ptr] <= iserdes_rd1[BYTE_LANE_WIDTH-1:BYTE_LANE_WIDTH/2];
memory_fd1_0[wr_ptr] <= iserdes_fd1[BYTE_LANE_WIDTH/2-1:0];
memory_fd1_1[wr_ptr] <= iserdes_fd1[BYTE_LANE_WIDTH-1:BYTE_LANE_WIDTH/2];
end
assign rise_data0 = {memory_rd0_1[rd_ptr],memory_rd0_0[rd_ptr]};
assign fall_data0 = {memory_fd0_1[rd_ptr],memory_fd0_0[rd_ptr]};
assign rise_data1 = {memory_rd1_1[rd_ptr],memory_rd1_0[rd_ptr]};
assign fall_data1 = {memory_fd1_1[rd_ptr],memory_fd1_0[rd_ptr]};
Revision History
07/25/2012 - Initial release
AR# 50752 | |
---|---|
Date | 01/16/2013 |
Status | Active |
Type | Known Issues |
Devices | |
IP |