Description

Solution

Thefollowing stepsdescribe how to customize the SEM IP, generate the example design files, and add these files to your Vivado tools project.

1. From the Vivado IP Catalog, browse to FPGA Features and Design -> Soft Error Mitigation -> Soft Error Mitigation. [refer to image: 1_IP_Catalog], and double-click the IP to open the customization GUI.

1_IP_Catalog.PNG

2. For this example, the IP has been customized to enable Error Classification. All other options are left as default. Click OK to continue. [refer to image: 2_classification_gui]

2_classification_gui.PNG

3. Right-click on the ".xci" file in the Sources window, Hierarchy tab. Select Generate. [refer to image: 3_generate_targets]

3_generate_targets.png

4. Select all available targets for generation, which will generate the selected target types to disk. For SEM IP, the available targets are: Synthesis, Examples, and Instantiation Template. Click OK to continue.[refer to image: 4_targets]

4_targets.PNG

5. In the Sources window, select the IP Sources tab and expand the list of sources. The generated targets are shown here. [refer to image: 5_IP_sources] Left-click on any of the generated files under Examples, then find the Location of the file in the Generated Data Properties window.The file path will be used in the next step to add the SEM example design files to the Vivado tools project.

5_IP_sources.PNG

6. In the Sources window, return to the Hierarchy tab. Click on Add Sources in the Flow Navigator window to open the Add Sources wizard. Leave Add or Create Design Sources selected, and click Next.Click Add Files to browse to the location on the disk where the example design files are stored.Select all of the example design files, then click OK. [refer to image 6_add_sources]. Click Finish to continue, and exit the Add Sources wizard. In the Sources window, Hierarchy tab, the hierarchy of files in the Vivado tools project will update to reflect the inclusion of the example design files.

6_add_sources.PNG

7. In the Sources window, select the IP Sources tab, and locate the example XDC file, <component name>_sem_example.xdc. Double-click on the XDC file to open it. Copy the constraints to the user XDC file within the project. Uncomment the template for the I/O placement constraints, and specify the desired pin location for each signal.

The SEM IP has now been successfully added to the Vivado tools project. For more information on using the SEM IP in Vivado, refer to the SEM IP Product Guide, PG036. This product guide provides additional instructions, including how to generate the essential bit files in the Vivado tool and execute the provided makedata.tcl script to generate the external memory programming file as needed for the Classification and Correction by Replace Features of the IP.

For more information on using theVivado tool, refer to the Vivado Getting Started Guide.