We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50795

LogiCORE IP XAUI, Vivado, 7 Series - Timing failures might occur in XAUI Example Design


Timing failures might occur in the XAUI core Example Design if targeting 7 series FPGAs.


To work around this issue, the core can be constrained to be placed close to the selected GTs.

In the XDC file, one of the following area groups can be used:

A.  Create a slice range area group:

create_pblock pblock_xaui_block
add_cells_to_pblock [get_pblocks pblock_xaui_block]  [get_cells -quiet [list xaui_block]]
resize_pblock [get_pblocks pblock_xaui_block] -add {SLICE_XnnnYnnn:SLICE_XnnnYnnn}

(Where SLICE_XnnnYnnn:SLICE_XnnnYnnn are the appropriate ranges to place the core adjacent to the GT).

B. If a clock region is desired instead of a slice range, the following could be used:

create_pblock pblock_xaui_block
add_cells_to_pblock [get_pblocks pblock_xaui_block]  [get_cells -quiet [list xaui_block]] 
resize_pblock [get_pblocks pblock_xaui_block] -add {CLOCKREGION_X1Y2}

(Where XnYn are the appropriate numbers for the clock region neighboring the GT).
AR# 50795
Date 11/06/2014
Status Active
Type General Article
  • XAUI