Timing failures might occur in certain cases when using the Ten Gigabit Ethernet PCS/PMA v2.4 in Vivado 2012.2 for 7 series FPGAs.
To resolve potential failures and to improve timing and synthesis results (even if you are not experiencing failures), the following updates should be made to the XDC files:
change the following
create_clock -name RXOUTCLK_OUT -period 3.103 [get_pins * -hierarchical -filter {NAME =~ *RXOUTCLK_OUT}]
create_clock -name TXOUTCLK_OUT -period 3.103 [get_pins * -hierarchical -filter {NAME =~ *TXOUTCLK_OUT}]
to the following (if you are using GTX transceivers)
create_clock -name TXOUTCLK_OUT -period 3.103 [get_pins -of_objects [get_cells * -hierarchical -filter {REF_NAME=~ GTXE2_CHANNEL}] -filter {NAME =~ *TXOUTCLK}]
create_clock -name RXOUTCLK_OUT -period 3.103 [get_pins -of_objects [get_cells * -hierarchical -filter {REF_NAME=~ GTXE2_CHANNEL}] -filter {NAME =~ *RXOUTCLK}]
OR, to the following (if you are using GTH transceivers)
create_clock -name TXOUTCLK_OUT -period 3.103 [get_pins -of_objects [get_cells * -hierarchical -filter {REF_NAME=~ GTHE2_CHANNEL}] -filter {NAME =~ *TXOUTCLK}]
create_clock -name RXOUTCLK_OUT -period 3.103 [get_pins -of_objects [get_cells * -hierarchical -filter {REF_NAME=~ GTHE2_CHANNEL}] -filter {NAME =~ *RXOUTCLK}]
AR# 50809 | |
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Date | 09/15/2014 |
Status | Active |
Type | General Article |
IP |