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AR# 50821

14.7 ERROR:LIT:667 - Block 'MMCM_ADV symbol "physical_group_u_pll_test1/clkfbout/u_pll_test1/mmcm_adv_inst" has its target frequency, FVCO, out of range.


At the MAP stage, I am receiving the following error with my design:

ERROR:LIT:667 - Block 'MMCM_ADV symbol
   "physical_group_u_pll_test1/clkfbout/u_pll_test1/mmcm_adv_inst"' has its
   target frequency, FVCO, out of range. Valid FVCO range for speed grade "-2"
   is 600MHz - 1200MHz. The computed FCVO is a function of the input frequency
   CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F
   CLKIN_PERIOD attribute may have been set by ngdbuild based on the user
   specified PERIOD constraint. The current calculated FVCO is 2000.000000 MHz.
   Reference the V6 architecture Users Guide or search the Xilinx Answer Records
   database for the error code.



When an MMCM is generated in Coregen, some factors (Such as CLKFBOUT_MULT_F, CLKFBOUT_MULT_F) are fixed.

In the above example, the DRC check contains the following for FVCO:


CLKIN1_PERIOD is from the period constraint of UCF.

The cause of this error message, is that the period constraint for the input of MMCM must be different from the frequency set in Coregen.

When you use the correct period constraint for the input of MMCM, the issue is resolved. 


AR# 50821
Date 01/19/2015
Status Active
Type General Article
  • Virtex-6
  • ISE Design Suite - 13
  • ISE Design Suite - 14
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