Description

This Release Note and Known Issues Answer Record is for the LogiCORE IP Serial RapidIO Gen2 v1.5 which was released in the ISE 14.2 and Vivado 2012.2 design tools and contains the following information:

• New Features
• Supported Devices
• Resolved Issues
• Known Issues
• Other Information

For installation instructions, general CORE Generator tool known issues, and design tool requirements, see the IP Release Notes Guide.

Solution

New Features

ISE Design Suite

• ISE 14.2 design tools support
• Enhancements to the example design
• Timing improvements

Vivado Design Suite

• 2012.2 tool support
• Enhancements to the example design
• Timing improvements

Supported Devices

ISE Design Suite

The following device families are supported by the core for this release:

• Virtex-7 devices
• Virtex-7
• Virtex-7 -2G
• Virtex-7 HT/XT
• Virtex-7 Low Voltage (-2L)
• Kintex-7 devices
• Kintex-7
• Kintex-7 Low Voltage (-2L)
• Virtex-6 devices
• Virtex-6 CXT/LXT/SXT/HX
• Virtex-6 Lower Power (-1L) LXT/SXT

Vivado Design Suite

The following device families are supported by the core for this release.

• Virtex-7 devices
• Virtex-7
• Virtex-7 -2G
• Virtex-7 HT/XT
• Kintex-7 devices
• Kintex-7

Resolved Issues

ISE Design Suite

• (Xilinx Answer 47919) - Example design simulation fails when LCSBA is enabled and assigned it to a specific address
• (Xilinx Answer 50139) - 16-bit Device ID width not supported
• Synchronized registers in the statistics gatherer utility in the example design
• Timing improvements through out the LOG and PHY layers

Vivado Design Suite

• (Xilinx Answer 47411) - Malformed SRIO Synthesis Netlist when Hierarchy is set to 'rebuilt'
• (Xilinx Answer 47744) - IDLE2 Mode Not Supported
• (Xilinx Answer 47919) - Example design simulation fails when LCSBA is enabled and assigned to a specific address
• (Xilinx Answer 50139) - 16-bit Device ID width not supported
• Synchronized registers in the statistics gatherer utility in the example design
• Timing improvements through out the LOG and PHY layers

Known Issues

ISE Design Suite

• When the ChipScope tool is enabled for the example design, timing might not be met during the implementation process.
• (Xilinx Answer 50831) - Simulation failure under some specific configuration
• (Xilinx Answer 50675) - 7 Series GTX Wrapper Attributes Update
• (Xilinx Answer 50883) - Implementationmayfail with slack violation timing error
• (Xilinx Answer 50889) - Device ID is set to 8 bits even though 16 bit value is selected in the GUI
• (Xilinx Answer 53326) - Reading back the DeviceID always returns 0xFF instead of the value set in the Coregen GUI

Vivado Design Suite

• Hardware validation has not been performed. This release is a design tools release only, and should only be used for implementation and simulation analysis.
• ChipScope tool support has not been added under the Vivado design tools flow.
• (Xilinx Answer 50830) - CRITICALWARNING:[Common 17-54] The object 'port' does not have a property 'IOSTANDARD'
• (Xilinx Answer 50831) - Simulation failure under some specific configuration
• (Xilinx Answer 50832) - XSIM flow Support
• (Xilinx Answer 50675) - 7 Series GTX Wrapper Attributes Update
• (Xilinx Answer 50889) - Device ID is set to 8 bits even though 16-bit value is selected in the GUI
• (Xilinx Answer 53326) - Reading back the DeviceID always returns 0xFF instead of the value set in the Coregen GUI

Other Information

• Virtex-6, Kintex-7, Virtex-7 have all been validated with IES and GES silicon
  For more information on hardware validation, please contact Xilinx Technical Support by opening a WebCase at: http://www.xilinx.com/support/clearexpress/websupport.htm
• Some interoperability testing has been completed
• Testing remains ongoing

Revision History

07/25/2012 - Initial release
12/05/2012 - Added (Xilinx Answer 53326)

Linked Answer Records

Child Answer Records