We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50837

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.2 (ISE 14.2/Vivado 2012.2) - Some features in generated example design and testbench not verified


Version Found: v1.2
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The following are some features that are included in the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.2 Endpoint example design and test bench but have not been verified yet.

  • Message Transaction and Error Packet Generation from Testbench
  • Generation of Upstream Memory Requests which are initiated by writing Specified values into Expansion ROM registers


This is a known issue to be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
07/25/2012 - Initial release

AR# 50837
Date 07/27/2015
Status Active
Type Known Issues
  • ISE Design Suite - 14.2
  • Vivado Design Suite - 2012.2
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
Page Bookmarked