UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 50858: MIG Virtex-5 DDR2 Dual Rank - Incorrect Pre-charge issued when switching ranks causing data errors

AR# 50858

MIG Virtex-5 DDR2 Dual Rank - Incorrect Pre-charge issued when switching ranks causing data errors

Description

The Virtex-5 DDR2 Dual Rank design has been found to incorrectly issue a pre-charge when switching between ranks. Because the controller mistakenly sends the pre-charge, an activate is not sent to the closed location, causing data errors in both simulation and hardware. This issue will be seen in all MIG versions of the Virtex-5 dual rank design.

Solution

The issue found is within the bank management logic of the controller logic. A fix has been identified and fully tested. The issue and subsequent fix are displayed here:

50858.JPG



The fix and corresponding instructions can be downloaded from the link at the bottom of this answer record.

Attachments

Associated Attachments

Name File Size File Type
ar50858.zip 21 KB ZIP
AR# 50858
Date 03/02/2013
Status Active
Type Known Issues
Devices
  • Virtex-5
IP
  • MIG