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LogiCORE IP Tri-Mode Ethernet MAC v5.4, ISE, 7 Series - Input timing violations could occur in the example design for certain cases
When using the Tri-Mode Ethernet MAC v5.4 example design, setup or hold timing violations could occur for the GMII or RGMII offset in timing constraints.
Small timing violations have occurred for some configurations when targeting Artix-7, Zynq-7000, or Virtex-7 Low Power devices.
The product guide contains GMII and RGMII Input Setup/Hold Timing sections which provide guidance on meeting the setup and hold window depending on the selected physical interface.
LOC down the I/O as appropriate and follow the guidelines in the product guide to adjust IDELAY tap settings or PLL clock phase shift.
In the v5.5 core and later, Artix-7 and Zynq-7000 receive clocking is changed to use IDELAYs instead of PLL to improve the receive setup and hold window.
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