UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 50879: LogiCORE IP Initiator, Target v4.17 for PCI - Simulation fails with " ERROR: Master Abort" in IUS

AR# 50879

LogiCORE IP Initiator, Target v4.17 for PCI - Simulation fails with " ERROR: Master Abort" in IUS

Description

I am using the LogiCORE IP Initiator, Target v4.17 for PCI core.


When simulating this core in IUS with an ISE flow, it fails with an "ERROR: Master Abort" message.

Solution

This is a known issue in IUS for Virtex-5 architecture with an ISE 14.2 flow.

The issue does not exist in ModelSim.

AR# 50879
Date 10/16/2014
Status Active
Type Known Issues
Devices
  • Virtex-5
Tools
  • ISE Design Suite - 14.2
IP
  • 64-bit Initiator/Target for PCI
  • 32-bit Initiator/Target for PCI
Page Bookmarked