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AR# 50917

LogiCORE IP FIFO Generator - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE IP FIFO Generator.

The following information is listed for each version of the core:

    • General Information
    • New Features
    • Bug Fixes
    • Known Issues
    • Technical Support

Solution

General Information

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For the most recent updates to the IP installation instructions for this core, see:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
For software requirements, please go to the "Software Requirements" link on that page.

This file contains Release Notes for the Xilinx LogiCORE IP FIFO Generator solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm

LogiCORE IP Fifo Generator v9.3

New Features

ISE

  • ISE 14.3 design tools support
  • Clock Enable support for AXI4 Stream FIFO

Vivado

  • 2012.3 tools support
  • Clock Enable support for AXI4 Stream FIFO
  • IP level constraint for cross clock domain logic

Supported Devices

ISE - The following device families are supported by the core for this release:

  • All 7 series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • All Spartan-6 devices
  • All Virtex-5 devices
  • All Spartan-3 devices
  • All Virtex-4 devices

Vivado

  • All 7 series devices
  • Zynq-7000 devices

Resolved Issues

ISE

  • N/A

Vivado

  • N/A

Known Issues

ISE

The following are known issues for v9.3 of this core at time of release:

  • Importing an XCO file alters the XCO configurations
    Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
    into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
    page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

    CR 467240
    (Xilinx Answer 31379)
  • Status flags after the first write to Common Clock Built-in FIFO not guaranteed
    Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
    correct behavior of the FIFO status flags cannot be guaranteed after the first write.
    Work-around: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
    For more information and additional workaround see (Xilinx Answer 41099).

Vivado

The following are known issues for v9.3 of this core at time of release:

  • Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen.
    ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.

    CR 665836
LogiCORE IP FIFO Generator v9.2

New Features

ISE

  • ISE 14.2 design tools support
  • Accurate data count support for AXI4 Stream Packet FIFO

Vivado

  • 2012.2 tools support
  • Accurate data count support for AXI4 Stream Packet FIFO

Supported Devices

ISE

The following device families are supported by the core for this release:

  • All 7 series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • All Spartan-6 devices
  • All Virtex-5 devices
  • All Spartan-3 devices
  • All Virtex-4 devices

Vivado

  • All 7 series devices
  • Zynq-7000 devices

Resolved Issues

ISE

  • N/A

Vivado

  • N/A

Known Issues

ISE

The following are known issues for v9.2 of this core at time of release:

  • Importing an XCO file alters the XCO configurations
    Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
    into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
    page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

    CR 467240
    (Xilinx Answer 31379)
  • Status flags after the first write to Common Clock Built-in FIFO not guaranteed
    Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
    correct behavior of the FIFO status flags cannot be guaranteed after the first write.
    Work-around: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
    For more information and additional workaround see Answer Record 41099.

Vivado

  • Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen.
    ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.

    CR 665836

LogiCORE IP FIFO Generator v9.1

New Features

ISE

  • ISE 14.1 design tools support
  • Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support
  • Data width support up to 4096 for AXI FIFO
  • Support of programmable Full/Empty flags as sideband signals for AXI FIFO

Vivado

  • 2012.1 tools support
  • Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support
  • Data width support up to 4096 for AXI FIFO
  • Support of programmable Full/Empty flags as sideband signals for AXI FIFO

Supported Devices

ISE

The following device families are supported by the core for this release:

  • All 7 series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • All Spartan-6 devices
  • All Virtex-5 devices
  • All Spartan-3 devices
  • All Virtex-4 devices

Vivado

  • All 7 series devices
  • Zynq-7000 devices

Resolved Issues

ISE

  • N/A

Vivado

  • N/A

Known Issues

ISE

The following are known issues for v9.1 of this core at time of release:

  • Importing an XCO file alters the XCO configurations
    Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

    CR 467240
    (Xilinx Answer 31379)
  • Status flags after the first write to Common Clock Built-in FIFO not guaranteed
    Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, correct behavior of the FIFO status flags cannot be guaranteed after the first write.
    Work-around: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
    For more information and additional workaround see (Xilinx Answer 41099).

Vivado

  • N/A

LogiCORE IP FIFO Generator v8.4

New Features

  • ISE 13.4 design tools support
  • Packet FIFO feature addition
  • Support added for Virtex-7,Virtex-7 -2L,Virtex-7 -2G,Virtex-7 XT,Kintex-7,Kintex-7 -2L, Artix-7, Zynq-7000*

Bug Fixes

  • NA

Known Issues

  • (Xilinx Answer 45744) ISE 13.4 CORE Generator FIFO Generator v8.4- Not able to open core documentation in CORE Generator tool
  • (Xilinx Answer 31379) Cannot change read/write clock frequencies with Built-in FIFO when importing an XCO file.

LogiCORE IP FIFO Generator v8.3

New Features

  • 13.3 ISE design tools support
  • Virtex-6QL and Spartan-6Q device support

Bug Fixes

  • CR617397 - M_ACLK mapping for write response and read data channels is corrected

Known Issues

  • (Xilinx Answer 31379) - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
  • (Xilinx Answer 41099) - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, correct behavior of the FIFO status flags cannot be guaranteed after the first write.

LogiCORE IP FIFO Generator v8.2

New Features

  • ISE 13.2 design tools support
  • Kintex-7L, Virtex-7L, Artix-7, and Zynq device support

Bug Fixes

The FIFO Generator core and the behavioral models in AXI Streaming mode accept the data during reset (s_aresetn is low)

Known Issues

  • In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
  • CR617397 M_ACLK mapping for the write response and read data channel is incorrect. M_ACLK is mapped to the read side rather than the write

LogiCORE IP FIFO Generator v8.1

New Features

  • ISE 13.1 design tools support
  • Kintex-7 and Virtex-7 device support
  • Wiring Logic and Register Slice feature support for AXI4
  • Virtex-7, Kintex-7 devices supported

Bug Fixes

  • (Xilinx Answer 37201) The FIFO Generator GUI does not generate the core if the Family is Spartan-6, and FIFO Implementation Type is either Common or Independent Clock Block RAM, and the depth is 64K and the width is 36.

Known Issues

  • (Xilinx Answer 31379) In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

LogiCORE IP FIFO Generator v7.2

New Features

  • ISE 12.3 design tools support
  • AXI4 (AXI4-Stream, AXI4 and AXI4-Lite) Support (Spartan-6 and Virtex-6 devices only)

Bug Fixes

  • CR568630 In the FIFO Generator GUI, navigation buttons at the bottom are not accessible unless the screen resolution is set to 1600x1200 or 1900x1200.
  • CR570414 The FIFO Generator GUI does not generate the core if the depth is reduced after the data count option is selected.

Known Issues

  • (Xilinx Answer 31379) LogiCORE FIFO Generator v4.3 - Cannot change read/write clock frequencies with Built-in FIFO when importing an XCO file
  • (Xilinx Answer 37201) LogiCORE FIFO Generator 6.3 - Crashes when creating a 36 x65K core
  • (CR 467240) In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

LogiCORE IP FIFO Generator v6.2

Supported Devices

New Features

  • ISE 12.2 design tools support

Bug Fixes

  • CR 553279 In the FIFO Generator core, PROG_FULL does not assert when set to maximum threshold value.
  • CR 549673 In the FIFO Generator verilog behavioral model, PROG_EMPTY does not assert/de-assert when the threshold value is passed through parameter.
  • CR 563827 In the FIFO Generator GUI, read width is reset to write width when the component name is change.

Known Issues

  • (Xilinx Answer 31379) In the FIFO generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 coregen project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

LogiCORE IP FIFO Generator v6.1

New Features

  • ISE 12.1 design tools support
  • Spartan-6, Spartan-6 XA, Spartan-6L and Spartan-6Q device support
  • Virtex-6, Virtex-6L and Virtex-6Q device support

Bug Fixes

  • CR 533832 In the FIFO Generator behavioral models, write operations are blocked during reset.
  • CR 531566 In the FIFO Generator GUI, embedded register option is not available for 512 deep common clock built-in FIFO with ECC for Virtex-5, Virtex-6/6L devices.
  • CR 531444 In the FIFO Generator behavioral models, the assertion and de-assertion of DBITERR and SBITERR signals are not matching with the common clock Block RAM based FIFO with FWFT, embedded register and synchronous reset.

Known Issues

  • (Xilinx Answer 31379) CR 467240 In the FIFO generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

New Features

  • ISE 11.3 design tools support
  • Virtex-6 -L Lower-power and Virtex-6 HXT device support
  • Spartan-3A\-3A DSP Automotive device support

Bug Fixes

  • (Xilinx Answer 32737) CR 502500 - Virtex-5 - Use Dout Reset feature is not supported according to the User Guide, but it is available in the GUI
  • (Xilinx Answer 32739) CR 525051 - Last word not read out of FIFO using Virtex-6 device Built In FIFO
  • (Xilinx Answer 32988) CR 522794 - Virtex-6 device Built-In FIFOs targeting FIFO36E1 primitives fail to generate
  • (Xilinx Answer 33213) CR 525159 -The MSBs of DOUT are stuck at a fixed value.

Known Issues

FIFO Generator v5.2

New Features

  • ISE 11.2 design tools support
  • Virtex-6 and Spartan-6 device support

Bug Fixes

  • (Xilinx Answer 31381) CR 471467 and CR 473003 - Empty flag does not assert in Common Clock (block RAM based) behavioral model simulation
  • CR 518140 - FIFO generator user guide has incorrect description for Non-Symmetric Aspect Ratios.

Known Issues

  • Virtex-6 and Spartan-6 solutions are pending hardware validation
  • Software Support for the Virtex-6 Lower Power parts was added in this release, but FIFO Generator is not yet supported and cannot be generated from CORE Generator. In order to work around this issue, you can set your project to target
    an equivalent Virtex-6 LXT device which will allow you to generate a place holder IP that can be regenerated when support for the Virtex-6 Lower Power parts is added in 11.3.
  • (Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5
  • (Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
  • (Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur
  • (Xilinx Answer 20271) Simulation error occurs on RESET
  • (Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected
  • (Xilinx Answer 31379) When importing an XCO file, user cannot change read/write clock frequencies with Built-in FIFO
  • (Xilinx Answer 32740) Write Data Count is not cycle accurate in behavioral model for non symmetric aspect ratios of 1:4 and 1:8 when FWFT is used
  • (Xilinx Answer 32739) Last word not read out of FIFO using Virtex-6 Built In FIFO
  • (Xilinx Answer 32988) Virtex-6 Built-In FIFOs targeting FIFO36E1 primitives fail to generate

LogiCORE IP FIFO Generator v5.1

Supported Devices

New Features

  • ISE 11.1 design tools support
  • Option to select WR_RST/RD_RST for independent clock block RAM or distributed RAM FIFOs
  • ECC error injection support for Virtex-6 block RAM and built-in FIFOs
  • Enhanced the core to block write/read operation when reset is asserted

Bug Fixes

  • (Xilinx Answer 32032) CR 498565 - Why is FWFT not available for Distributed RAM configurations?
  • CR 448037- In the FIFO generator core, synchronous reset option is not available for Shift Register configuration
  • CR 476442 and CR 472517 - In the FIFO generator VHDL behavioral model, array lengths do not match while loading the design for simulation
  • CR 437899 - In the FIFO generator user guide, write order in figure 4-17 and 4-18 are not correct
  • CR 456488 - In the FIFO generator GUI, FIFO Read Depth reported incorrectly in GUI for FWFT w/Asymmetric Ports
  • CR 480033 - In the FIFO generator GUI, summary page does not explain MULT/BRAM routing contention for Spartan-3 devices

Known Issues

LogiCORE IP FIFO Generator v4.4

New Features

  • Option to enable/disable timing violations on cross clock domain registers
  • Enhanced data width support - up to 1024
  • Virtex-5 TXT device support
  • Summary of simulation model chosen and its limitations in FIFO generator CORE Generator GUI summary page

Bug Fixes

  • (Xilinx Answer 30221) Customization GUI incorrectly advertises FWFT support for certain configurations - CR 458157
  • (Xilinx Answer 30571) Synchronous reset (SRST) does not affect DOUT or EMPTY - CR 467318
  • CR 473545 - In the FIFO Generator User Guide, the behavior of the asynchronous reset is not clearly defined
  • CR 472155 - In the FIFO Generator User Guide, reset description in Table 2-4 does not clarify its behavior
  • CR 467555 - In the FIFO Generator User Guide, simultaneous assertion of FULL/EMPTY flag behavior for non built-in independent clock FIFO is not defined
  • CR 467514 - In the FIFO Generator User Guide, the behavior of the write operation for a FIFO with independent clock (Figure 4-6) is incorrect
  • CR 440839 - In the FIFO Generator GUI, depth selection for Virtex-5 built-in FIFO is incorrectly defined

Known Issues

LogiCORE IP FIFO Generator v4.3

New Features

  • ISE 10.1 design tools support
  • Option to enable or disable the embedded register for Virtex-5 built-in common clock FIFO.

Bug Fixes

  • (Xilinx Answer 29514) - CR 449605 - In the Verilog behavioral model, WR_DATA_COUNT behavior in asymmetric FWFT configurations is undefined
  • (Xilinx Answer 29581) - CR 450727 - In the Verilog behavioral model, the behavior of programmable full is incorrectly defined for common Clock Shift RAM
  • (Xilinx Answer 29513) - CR 449899 - In the VHDL behavioral model, the behavior of underflow flag during reset is undefined
  • CR 454156 - In the VHDL behavioral model, DOUT is reset even when use_dout_reset is false. The work-around for pre-v4.3 cores is to use the Verilog or Structural model
  • CR 448828 - In the GUI, Single Programmable Empty assert and Multiple Programmable Empty assert and negate max values are incorrect. The work-around for pre-v4.3 cores is for the user to limit the "Single Prog Empty" to a maximum of (Read Depth - 1), the "Multiple Prog Empty" Assert to a max of (Read Depth - 2), and the "Multiple Prog Empty" Negate to a max of (Read Depth - 1).

Known Issues

  • (Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5
  • (Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
  • (Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur
  • (Xilinx Answer 20271) Simulation error occurs on RESET
  • (Xilinx Answer 30221) Customization GUI incorrectly advertises FWFT support for certain configurations
  • (Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected
  • (Xilinx Answer 30571) Synchronous reset (SRST) does not affect DOUT or EMPTY
  • (Xilinx Answer 31379) When importing an XCO file user cannot change read/write clock frequencies with Built-in FIFO
  • (Xilinx Answer 31380) The first word does not fall through in structural simulation of a Common Clock BRAM with FWFT
  • (Xilinx Answer 31381) Empty flag does not assert in Common Clock (BRAM based) behavioral model simulation
  • The "Option to disable timing violations on cross clock domain registers" mentioned in the "readme" and "Version Information" files generated with the core has been pulled from the FIFO v4.3 release.

LogiCORE IP FIFO Generator v4.2

New Features

  • Support for First-Word-Fall-Through read mode for Block RAM and Distributed RAM Common Clock FIFOs
  • Option to not reset DOUT when reset signal is asserted

Bug Fixes

  • (Xilinx Answer 29137) - CR 431975 - "WARNING:Ngdbuild:452 - logical net 'u1/BU2/prog_*_thresh_assert<*>' has
  • no driver"
  • (Xilinx Answer 29173) - - CR 445849 - In VHDL behavioral model simulation, DOUT powers up as 'x' until the first word is presented
  • (Xilinx Answer 29172) - CR 445381- In behavioral model simulation, powerup values for DOUT and VALID are undefined
  • (Xilinx Answer 29228) - - CR 448672 Programmable Full and Empty flags do not work correctly when FIFO is full for Common Clock Block RAM and Distributed RAM FIFOs
  • CR 447282 - Write data count for Verilog behavior model reports incorrect and abnormally high values at or near empty (Independent Clock FIFOs only)
  • CR 448521 - Read data count behaves incorrectly when not at maximum width and FIFO is configured as First-Word-Fall-Through

Known Issues

New Features

  • ECC support added to Virtex-5 block RAM-based FIFO configurations
  • Full range of data count widths now supported for nonsymmetric aspect ratio configurations
  • Option to define reset value for full condition flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, distributed RAM and shift RAM-based FIFO configurations only
  • Support added for use of embedded output registers in block RAM FIFO configurations (Virtex-4 and Virtex-5 only)

Bug Fixes

  • CR 433738: GUI reports incorrect number of built-in FIFOs primitive used
  • CR 435835: Programmable Full flag is always asserted even when FIFO is empty as the result of an incorrect threshold setting
  • CR 338260: Map errors out with "ERROR:LIT:250 Pins WEA), WEA1, WEA2, WEA# of RAMB16 symbol "physical..." do not share the same signal."
  • CR 436886: Write Data Count and Read Data Count overestimate the number of words written or read when core is configured with this combination of options:
    • First-Word-Fall-Through
    • Accurate data count using extra logic
    • Nonsymmetric port aspect ratios
  • CR 433637: SBITERR and DBITERR outputs are not driven in behavior models.
  • CR 43392: Maximum programmable empty threshold negate value is incorrect.
  • CR 435874: Programmable full flag behavior is incorrect when the core is configured with this combination of options:
    • FWFT
    • nonsymmetric port aspect ratio
    • single or multiple programmable full threshold input port.
  • CR 443569: Programmable empty flag stuck high when the core is configured with this combination of options:
    • block or distributed RAM FIFO
    • single or multiple programmable empty threshold input port.

Known Issues

  • (Xilinx Answer 29172) In behavioral simulation, power up value for DOUT and VALID signals are undefined
  • (Xilinx Answer 29173) In VHDL behavioral simulation, DOUT powerup as "x" until the first word falls out
  • (Xilinx Answer 24003) NCELab issues warnings: "memory index out of declared bounds" in simprims_ver_virtex5_source.v or unisim_ver_virtex5_source.v during Verilog structural and timing simulations in NCSIM for Virtex-5 block RAM FIFOs. The simulation will be successful, and the warnings can be ignored
  • (Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO
  • (Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"
  • (Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."
  • (Xilinx Answer 29137) "WARNING:Ngdbuild:452 - logical net 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during NgdBuild although programmable empty or full is not selected. Warnings can be safely ignored.

Device Issues

Please note the Virtex-4 and Virtex-5 Errata posted at: http://www.xilinx.com/support/mysupport.htm.

The FIFO Generator Core with block RAM configuration is subject to all block RAM issues listed in the errata.

LogiCORE IP FIFO Generator v3.3

New Features

  • ECC support for Virtex-5 built-in FIFO configuration

Bug Fixes

  • CR 423076: If the reset pin is not selected, the Reset Type text on page 6 of the GUI Summary is displayed incorrectly as "Asynchronous" instead of "Not Selected"
  • CR 422495: Core cannot be generated for Independent Clock Block RAM FIFOs with input_depth=16 and output_depth=128, or input_depth=128 and output_depth=16

Known Issues

  • (Xilinx Answer 24802)"Estimated FIFO usage" feature in the last page of the GUI is not accurate when ECC feature is enabled
  • (Xilinx Answer 24003) NCELab issues warnings: "memory index out of declared bounds" in simprims_ver_virtex5_source.v or unisim_ver_virtex5_source.v during Verilog structural and timing simulations in NCSIM for Virtex-5 block RAM FIFOs. The simulation will be successful, and the warnings can be ignored
  • (Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO
  • (Xilinx Answer 20278) PROG_EMPTY and PROG_FULL can produce false-assertions
  • (Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"
  • (Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."

Device Issues

Please note the Virtex-4 and Virtex-5 Errata posted at: http://www.xilinx.com/support/mysupport.htm.

The FIFO Generator Core with block RAM configuration is subject to all block RAM issues listed in the errata.

LogiCORE IP FIFO Generator v3.2

New Features

  • Virtex-4 XA, Spartan-3E XA, Spartan-3 XA and Spartan-3A device support added
  • Support for synchronous reset in common clock Block RAM and Distributed RAM implementations

Bug Fixes

  • CR 423373: In v3.2, Synchronous reset feature is implemented for Common clock BRAM and DRAM. In order for the FIFO to start up at a valid state at power-up (to be able to write to the FIFO on the very first clock edge), the flags now power up at an "synchronous reset" state. Please refer to the User Guide for details about the new power-up and reset values.
  • CR 422741: VHDL Behavioral model simulation fails with following message: Failure: FAILURE: Use of behavioral models for Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information. This failure was seen even for Distributed RAM and Block RAM type, and for Virtex-2.
  • CR 415411: VHDL Behavioral model simulation fails with a message, "Array lengths do not match", for the WR_DATA_COUNT flag for a First-Word-Fall-Through FIFO with Asymmetric Ports and "Use Extra Logic " option.
  • CR 419555: Verilog Behavioral model simulation of a First-Word-Fall-Through FIFO with Independent Clocks asserts the UNDERFLOW flags unexpectedly.
  • CR 235547: For Virtex-5 , Independent Clock, Built-in-FIFO, the programmable empty negate threshold was computed differently than the assert threshold.
  • CR 235545: Data count width defaults to an invalid value when the "Use extra logic" option for First-Word-Fall-Through is checked , then subsequently unchecked.

Known Issues

  • (Xilinx Answer 24002) For Block RAM and Distributed RAM FIFO, if the reset pin is not chosen, the reset type text in page 6 of the GUI Summary is displayed incorrectly as "Asynchronous" instead of "Not Selected".
  • (Xilinx Answer 24003) NCELab issues warnings: "memory index out of declared bounds" in simprims_ver_virtex5_source.v or unisim_ver_virtex5_source.v during Verilog structural and timing simulations in NCSIM for Virtex-5 block RAM FIFOs. The simulation will be successful and the warnings can be ignored.
  • (Xilinx Answer 24018) When running timing simulation for Virtex-5 design containing FIFO Generator built with Build-In-Fifo, the user might receive simulation error about TIEOFFREGCEAL connection problem
  • (Xilinx Answer 24019) Core cannot be generated for Independent Clock Block RAM FIFOs with input_depth=16 and output_depth=128 or input_depth=128 and output_depth=16
  • (Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO
  • (Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"
  • (Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."

Device Issues

Please note the Virtex-5 Errata posted at: http://www.xilinx.com/support/mysupport.htm.

FIFO Generator core with block RAM configuration is subject to all block RAM issues listed in the errata.

LogiCORE IP FIFO Generator v3.1

New Features

  • Support added for Virtex-5
  • Support added for ISE 8.2i
  • Uses Block Memory Generator Core in block-memory-based implementations for more efficient block memory utilization in the Spartan-3, Virtex-II, Virtex-4, and Virtex-5 architectures

Bug Fixes

  • (Xilinx Answer 22462) Incorrect status flag behavior issue in Virtex-4 FIFO16-based implementations. The fix supports FIFOs created using single FIFO16 primitive instantiations only.

Known Issues

LogiCORE IP FIFO Generator v2.2

New Features

  • Support added for using Built-in FIFO flags when constructing a FIFO from Virtex-4 built-in FIFO primitives.
  • Improved GUI to make "FWFT" feature more visible.

Bug Fixes

  • None

Documentation Changes

  • Modified use of the term "latency" to improve accuracy, consistency, and readability
  • Modified documents to accommodate GUI change on FWFT feature which used to be called "Registered Outputs" option

Known Issues

  • In addition to the data sheet, the User Guide is available for the FIFO Generator. To access the User Guide, generate the FIFO Generator v2.2 Core and search for "fifo_generator_ug175.pdf" in your COREGen project directory.
  • When using Virtex-4 FIFO16 type, the behavioral model might not show true latency on the outputs. In this case, it is strongly recommended that you use Structural simulation model. Refer to User Guide chapter on "Simulating Your Design."
  • (Xilinx Answer 20278) In a FIFO16-based FIFO Generator implementation, when the output depth is larger than the selected Input Depth, it is possible for PROG_EMPTY and PROG_FULL to produce false-assert values if the Programmable Empty or Programmable Full thresholds are near the limits of their range.
  • (Xilinx Answer 20291) During simulation, you might receive setup and hold time violations.
  • (Xilinx Answer 20271) When using Independent clocks with Block Memory type, you might see an error during back-annotated simulation (gate-level and timing) at the reset.
  • (Xilinx Answer 22014) Full width of data count is not available.

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support, Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

AR# 50917
Date Created 11/21/2012
Last Updated 02/12/2013
Status Active
Type Release Notes
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite
IP
  • FIFO Generator