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Xilinx SelectIO Solution Center

The SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design with SelectIO or troubleshooting a problem, use the SelectIO solution center to guide you to the right information.

Design Assistant

Xilinx SelectIO Solution Center - Design Assistant

The Design Assistant will walk you through the recommended design flow for designing with Xilinx SelectIO pins, while debugging commonly encountered issues. 

The Design Assistant will not only provide useful design and troubleshoot information, but also point you to the exact documentation you need to read to help you design efficiently with Xilinx SelectIO.

Note: This article is part of the Xilinx SelectIO Solution Center (Xilinx Answer 50924).

The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


The SelectIO Design Assistant is broken into sections (though they overlap). Please choose the section most related to your question or query.

This will ensure that the SelectIO Design Assistant points you to the information you need to continually move forward with your design.


IO Specifications and Performance:

(Xilinx Answer 47284) addresses questions on factors affecting performance:

  • Single-ended, Differential, and Pseudo-differential (Complimentary single-ended) I/O standards
  • SelectIO performance-related specifications provided in Xilinx data sheets

Termination and SelectIO:

(Xilinx Answer 47225) addresses questions on terminating transmission lines:

  • Basics of transmission lines
  • The types of termination depending on the I/O standard
  • How to setup optional internal termination in a design
  • Debugging issues with internal terminations


Board Level Debug

(Xilinx Answer 50537) addresses questions on debugging signal integrity issues:

  • SSO/SSN - Simultaneously Switching Output/Noise
  • Debugging issues with reflections or ringing
  • Debugging issues with data eyes
  • Debugging issues with signals not crossing expected thresholds


IO settings in the Xilinx Tools

(Xilinx Answer 47368) addresses questions on IOSTANDARDs

  • Types of IOSTANDARDs
  • Interfacing with Various IOSTANDARDs


Signal Integrity Simulations

(Xilinx Answer 50644) addresses questions on IBIS Models & Simulation

  • What information is contained in a IBIS models
  • Known issues with Xilinx IBIS models


IO Electrical Reliability

(Xilinx Answer 51834) addresses questions on the following:

  • Over driving I/Os - undershoot and overshoot
  • Hot swapping/plugging
  • Power sequencing and the I/O state during powering and configuration

Documentation

Xilinx SelectIO Solution Center - Documentation

Please refer to the following documentation when using SelectIO

Note: This article is part of the Xilinx SelectIO Solution Center (Xilinx Answer 50924).

The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


The two main sources of documentation for SelectIO are the DC and Switching Characteristics Data Sheet, and the SelectIO User Guide (note that for older devices, SelectIO was a chapter in the family User Guide).

The DC and Switching Characteristics Data Sheet contains tables of Input and Output Voltage Thresholds.

The SelectIO User Guides are invaluable for SelectIO information including:

  • Details of all of the supported IOSTANDARDs
  • The expected termination for each IOSTANDARD
  • The voltage requirements (Vcco and Vref)
  • Details on which attributes are supported for each IOSTANDARD
  • Details on how to combine IOSTANDARDs in a bank
  • DCI and DCI cascading information


Zynq UltraScale+ MPSoC SelectIO Documentation:

(UG571)UltraScale Architecture SelectIO User Guide
(UG1085)Zynq UltraScale+ MPSoC TRM (There are descriptions for all the MIO peripheral signaling)
(DS925)Zynq UltraScale+ MPSoC DC and AC Switching Characteristics Data Sheet

UltraScale+ SelectIO Documentation:

(UG571)UltraScale Architecture SelectIO User Guide
(DS922)Kintex UltraScale+ DC and AC Switching Characteristics Data Sheet
(DS923)Virtex UltraScale+ DC and AC Switching Characteristics Data Sheet

UltraScale SelectIO Documentation:

(UG571)UltraScale Architecture SelectIO User Guide
(DS892)Kintex UltraScale DC and AC Switching Characteristics Data Sheet
(DS893)Virtex UltraScale DC and AC Switching Characteristics Data Sheet

Zynq-7000 AP SoC SelectIO Documentation:

(UG471)7 Series SelectIO User Guide
(UG585)Zynq TRM (There are descriptions for all the MIO peripheral signaling)
(DS187)ZC7007S/7012S/7014S/7010/7015/7020 DC and AC Switching Characteristics Data Sheet
(DS191)ZC7030/7030/7045/7100 DC and AC Switching Characteristics Data Sheet

7 Series SelectIO Documentation:

(UG471)7 Series SelectIO User Guide
(DS181)Artix-7 DC and AC Switching Characteristics Data Sheet
(DS182)Kintex-7 DC and AC Switching Characteristics Data Sheet
(DS183)Virtex-7 DC and AC Switching Characteristics Data Sheet

Virtex-6 SelectIO Documentation:

(UG361)Virtex-6 SelectIO User Guide
(DS186)Virtex-6 DC and AC Switching Characteristics Data Sheet

Spartan-6 SelectIO Documentation:

(UG381)Spartan-6 SelectIO User Guide
(DS162)Spartan-6 DC and AC Switching Characteristics Data Sheet

Virtex-5 SelectIO Documentation:

(UG190)Virtex-5 Family User Guide
(DS202)Spartan-6 DC and AC Switching Characteristics Data Sheet

Spartan-3 SelectIO Documentation:

(UG331)Spartan-3 Family User Guide
(DS099)Spartan-3 DC and AC Switching Characteristics Data Sheet
(DS529)Spartan-3A DC and AC Switching Characteristics Data Sheet
(DS706)Spartan-3A Extended DC and AC Switching Characteristics Data Sheet
(DS557)Spartan-3AN DC and AC Switching Characteristics Data Sheet
(DS312)Spartan-3E DC and AC Switching Characteristics Data Sheet

Design Advisories

Xilinx SelectIO Solution Center - Design Advisory

The following Article lists the current Design Advisories from Xilinx that relate to SelectIO.

Note: This article is part of (Xilinx Answer 50924) the Xilinx SelectIO Solution Center. The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


Design Advisory List


Zynq UltraScale+ MPSoC

(Xilinx Answer 66944)Design Advisory for Zynq UltraScale+ MPSoC - Updated package pinouts relative to Xilinx.com since April 5th, 2016 


UltraScale


(Xilinx Answer 65998)Design Advisory - System Monitor and PCI Express:  I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 I/O pins have lower than expected Pin voltage levels 
(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements

Artix-7 

(Xilinx Answer 58162)Design Advisory for Artix-7 FPGA Wire-bond Package Devices - SelectIO prohibits pin list when GTP Transceivers are used 

Spartan-6 

(Xilinx Answer 35237)Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines
(Xilinx Answer 40818) - Spartan-6 INTERM_XX not being appropriately Turned On in BitGen for Spartan-6 FPGA inputs


Sign up For Design Advisories and Emerging Issues:

The best way to keep up to date with design advisories from Xilinx and learn about emerging issues is to sign up to alerts via your Xilinx.com account.

For a step-by-step guide to this please see the following Answer Record:

(Xilinx Answer 18683)


Top Issues

Xilinx SelectIO Solution Center - Top Issues

The following Articles cover current known issues as well as commonly asked questions related to SelectIO.

Note: This article is part of Xilinx SelectIO Solution Center (Xilinx Answer 50924). The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


Top Issues

(Xilinx Answer 21632)How to include pkg file in IBIS simulation
(Xilinx Answer 16830)Interfacing LVDS25, LVDS33 and LVPECL
(Xilinx Answer 11906)Is Vcco and Vref required on unpowered bank
(Xilinx Answer 19146)Are Spartan-3/3E I/Os 5V tolerant?
(Xilinx Answer 40416)6 Series - Hot Swap Support
(Xilinx Answer 9048)Which pins have clamp diodes?

7 Series Specific Issues

(Xilinx Answer 37347)Driving I/Os of unpowered devices
(Xilinx Answer 40191)Compatibility between LVDS powered at 1.8V and 2.5V
(Xilinx Answer 41408)How place LVDS in High performance banks
(Xilinx Answer 41615)7 Series - Required IOSTANDARD and LOC constraints on all I/O


Spartan-6 Specific Issues

(Xilinx Answer 35697)Missing UNTUNED IOSTANDARDs from Spartan-6 IBIS models
(Xilinx Answer 36100)Missing Left/Right LVDS from Spartan-6 IBIS models
(Xilinx Answer 35713)Does LVPECL support DIFF_TERM
(Xilinx Answer 35696)SSO Limit - Noise margin relationship

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