The Design Assistant will walk you through the recommended design flow for designing with Xilinx SelectIO pins, while debugging commonly encountered issues.
The Design Assistant will not only provide useful design and troubleshoot information, but also point you to the exact documentation you need to read to help you design efficiently with Xilinx SelectIO.
Note: This article is part of the Xilinx SelectIO Solution Center (Xilinx Answer 50924).
The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.
Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.
The SelectIO Design Assistant is broken into sections (though they overlap). Please choose the section most related to your question or query.
This will ensure that the SelectIO Design Assistant points you to the information you need to continually move forward with your design.
IO Specifications and Performance:
(Xilinx Answer 47284) addresses questions on factors affecting performance:
Termination and SelectIO:
(Xilinx Answer 47225) addresses questions on terminating transmission lines:
Board Level Debug
(Xilinx Answer 50537) addresses questions on debugging signal integrity issues:
IO settings in the Xilinx Tools
(Xilinx Answer 47368) addresses questions on IOSTANDARDs
Signal Integrity Simulations
(Xilinx Answer 50644) addresses questions on IBIS Models & Simulation
IO Electrical Reliability
(Xilinx Answer 51834) addresses questions on the following: