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AR# 50931

Xilinx SelectIO Solution Center - Top Issues

Description

The following Articles cover current known issues as well as commonly asked questions related to SelectIO.

Note: This article is part of Xilinx SelectIO Solution Center (Xilinx Answer 50924). The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.

Solution

Top Issues

(Xilinx Answer 21632)How to include pkg file in IBIS simulation
(Xilinx Answer 16830)Interfacing LVDS25, LVDS33 and LVPECL
(Xilinx Answer 11906)Is Vcco and Vref required on unpowered bank
(Xilinx Answer 19146)Are Spartan-3/3E I/Os 5V tolerant?
(Xilinx Answer 40416)6 Series - Hot Swap Support
(Xilinx Answer 9048)Which pins have clamp diodes?

7 Series Specific Issues

(Xilinx Answer 37347)Driving I/Os of unpowered devices
(Xilinx Answer 40191)Compatibility between LVDS powered at 1.8V and 2.5V
(Xilinx Answer 41408)How place LVDS in High performance banks
(Xilinx Answer 41615)7 Series - Required IOSTANDARD and LOC constraints on all I/O


Spartan-6 Specific Issues

(Xilinx Answer 35697)Missing UNTUNED IOSTANDARDs from Spartan-6 IBIS models
(Xilinx Answer 36100)Missing Left/Right LVDS from Spartan-6 IBIS models
(Xilinx Answer 35713)Does LVPECL support DIFF_TERM
(Xilinx Answer 35696)SSO Limit - Noise margin relationship

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
50924 Xilinx SelectIO Solution Center N/A N/A
AR# 50931
Date 06/02/2017
Status Active
Type Solution Center
Devices
  • FPGA Device Families
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