The following Article lists the current Design Advisories from Xilinx that relate to SelectIO.
Note: This article is part of (Xilinx Answer 50924) the Xilinx SelectIO Solution Center. The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.
Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.
Design Advisory List
Zynq UltraScale+ MPSoC
|(Xilinx Answer 66944)||Design Advisory for Zynq UltraScale+ MPSoC - Updated package pinouts relative to Xilinx.com since April 5th, 2016 |
|(Xilinx Answer 65998)||Design Advisory - System Monitor and PCI Express: I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 I/O pins have lower than expected Pin voltage levels|
|(Xilinx Answer 62483)||Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements|
|(Xilinx Answer 58162)||Design Advisory for Artix-7 FPGA Wire-bond Package Devices - SelectIO prohibits pin list when GTP Transceivers are used |
|(Xilinx Answer 35237)||Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines|
|(Xilinx Answer 40818)||- Spartan-6 INTERM_XX not being appropriately Turned On in BitGen for Spartan-6 FPGA inputs|
Sign up For Design Advisories and Emerging Issues:
The best way to keep up to date with design advisories from Xilinx and learn about emerging issues is to sign up to alerts via your Xilinx.com account.
For a step-by-step guide to this please see the following Answer Record: