We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50955

SelectIO Design Assistant: IBIS Models & Simulation - IBIS Model Limitations


This Answer Record outline some of the limitations of IBIS models.

IBIS models are increasingly used to an assist in PCB planning and debug issues with board level signal integrity. 

They are a powerful tool in re-creating issues commonly seen on customer boards. However there are some limitations that this Answer Record will cover.

This article is part of the Design Assistant section (Xilinx Answer 50926) of the SelectIO Solution Centre (Xilinx Answer 50924).



IBIS does not support measuring the delay through the I/O buffers from the pin to internal fabric and vice versa. In the device datasheets we specify this as Tiopi and Tioop.

Tiopi represents the propagation delay from the IOB pad through the input buffer to the I-pin of an IOB pad. Tioop represents the propagation delay from the O pin to the IOB pad through the output buffer of an IOB pad.

The IBIS simulation will not provide any information on these parameters, however the Measurement Methodology for these parameters are contained within the IBIS model (Vmeas, Cref, Rref and Vref)

3-Stated I/Os:

IBIS does not support modeling the behavior of a 3-stated I/O, for example what voltage level is on the output or what the effect on the other devices on the line are when the driver is 3-stated. It is not possible to set up an IBIS simulation that has a driver that is tri-stated.

SSN Effects:

In many Hardware debug situations where it appears that there are RX/TX errors occurring, one common aspect of the debug process is to check if simultaneously switching output drivers are causing variations in the power and ground rails that is then coupled onto the signal. 

This can cause the data to be transmitted and received incorrectly in hardware. IBIS simulation cannot model SSN effects which means that there could be a situation where an IBIS simulation shows good signal quality but the hardware still fails.

In UltraScale+ devices, support for IBIS 5.x has been added. This version of IBIS can be used for power aware simulations.

Power Supply Variation

It is possible to change some of the power supply values in the simulation. However it is not possible for a user to have a time varying voltage in the IBIS simulation tool and it is not possible to superimpose a random noise source onto the supply or ground rails. As a result, the simulation will not take into account the quality of the rails. 

There is also no way to de-rate the performance of the other rails on the device such as VCCAUX/VCCINT. 

In some cases, VCCAUX is used to power I/O circuitry. For 7 Series devices, there are special models dedicated to using VCCAUX_IO set to 2V for higher performance. There are specific models for the VCCAUX_IO = 2.0V, with AUX20 in the title, for example HSTL_I_DCI_18_S_AUX20_HP_O.

Floating I/O Pins:

IBIS does not support simulating the effect of not connecting a signal to an input, in order to simulate situations like hot swapping. 

The simulator requires all input pins to be connected so the IBIS models cannot be used to simulate a floating scenario.

Missing rails:

IBIS does not support simulating the effect of turning off a VCCO rail and still applying signals to the input of the I/O. 

IBIS models cannot give any information on this mode of operation. In the HyperLynx tool, the simulation will not run if the supply is turned off or set to 0 in the model.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
50644 SelectIO Design Assistant: IBIS Models & Simulation N/A N/A
AR# 50955
Date 06/02/2017
Status Active
Type Solution Center
  • FPGA Device Families
Page Bookmarked