This Article will provide an introduction to writing out custom IBIS models from a user design.
Xilinx Tools allow users to generate an IBIS model that is specific to their own design.
This model will contain the proper package parasitics for the I/Os, making the simulation more accurate.
Each tool flow contains a function for writing out an IBIS model for the design.
In ISE IBIS Writer is used to generate the IBIS model for the design. In PlanAhead / Vivado there is a process known as write_ibis for accomplishing this task.
Write_IBIS Process in PlanAhead / Vivado.
In PlanAhead/Vivado you can use the write_ibis command to write the IBIS model. The main advantage of this flow is that it does not require an NCD file.
This process can be run at the I/O pin planning stage, so the board level simulations are not dependent on having a near complete design.
The following screenshot shows how the IBIS model can be written out in PlanAhead/ Vivado.
The options for write_ibis are
The process can also be run from the Tcl console. Here is an example of the Tcl Syntax.
write_ibis C:/work/planAhead_testcases/io_1.ibs -truncate 40 -force
ISE IBIS Writer:
IBIS Writer is the tool used from the ISE flow to generate a design specific IBIS model. IBIS Writer requires a design source file as input.
For FPGA designs, this is a physical description of the design in the form of a Native Circuit Description (NCD) file with a .ncd file extension.
IBIS Writer can be launched from the command line or via the ISE GUI. The GUI option looks like this.
You can set options within IBIS Writer to do the following: