I generated the source files for the IP core(s) in my project, but the HDL is not created in the language specified in with the Target Language setting.
How do I specify what language I want an IP core to be generated in when I choose an item in the IP Catalog?
For example, in my project settings I have specified the Target Language as Verilog. I create a PCIe or Clocking Wizard core and the files are all Verilog. I create a FIFO or a block RAM using the Block Mem Gen and the files are all VHDL.
Is this expected behavior? Can I change the output HDL language of an IP core?
One of the main differences between the CORE Generator tool and the Vivado IP Catalog generation of cores is the files that are delivered for a core.
The majority of LogiCORE IP have their synthesizable IP core sources in a single language (i.e., VHDL or Verilog). Some IP cores will deliver synthesizable sources in either VHDL or Verilog (e.g., most IP Wizards will deliver an HDL wrapper on top of Xilinx device primitives).
The Target Language setting is used to:
Note: If creating a new project in the New Project Window (NPW), Add Sources dialog box, you can change the values of Target language (and also Simulation language). If you change these settings in this dialog, they are "sticky". The next time you create a project, NPW will show the same values as the last time.
However, if you create a project, and then use the project settings dialog to change these values, these changes are not remembered the next time you create a project. In other words, the Add Sources dialog remembers its "own" setting of these property values, but not what was set via the project settings dialog.