Currently, there is no specified date to resolve this issue.
As part of the work-around, Xilinx recommends that you put writes and reads for the two different ports in separate always/process blocks.
This answer record will be updated when a permanent resolution is available.
| AR# 51088 | |
|---|---|
| Date | 04/03/2013 |
| Status | Active |
| Type | General Article |
| Tools |
|