A Cortex-A9 processor might deadlock when the execution of a write to a Strongly Ordered memory region is followed by the execution of a conditional LDREX instruction that fails its condition code check.
These are the required but not sufficient conditions for the problem to occur, as it is also dependent on specific timing conditions within the Cortex-A9 that are not directly controllable by software.
| Impact: | Minor. Use the software workaround. |
Work-around: | Add a DMB or DSB instruction between the write to the Strongly Ordered memory region and the conditional LDREX. |
Configurations Affected: | Systems that use the LDREX instruction. |
| Device Revision(s) Affected: | All, no plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record. |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47916 | Zynq-7000 AP SoC Devices - Silicon Revision Differences | N/A | N/A |
| AR# 51122 | |
|---|---|
| Date | 06/13/2018 |
| Status | Active |
| Type | Design Advisory |
| Devices | |