AR# 51164

Vivado - How can I define verilog Macros?

Description

How can I define Verilog Macros in Vivado Design Suite?

Solution

A Verilog macro can be defined as follows.

1. Add synthesis option "-verilog_define MACRO_NAME=MACRO_VALUE".

2. Define the Macros in one file, and set it as "Global Include" by right-clicking the file.

3. In Project Settings -> Language Options -> Generics/Parameters, you can override parameters but not macros of the design.

AR# 51164
Date 10/19/2012
Status Active
Type General Article
Tools