This answer record provides a downloadable MIG 7 Series DDR2/DDR3 PHY Only Design Guide in PDF format to enhance its usability. Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.
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Please download the MIG 7 Series DDR2/DDR3 PHY Only Design Guide (PDF) attached to the end of this solution.
The MIG 7 Series DDR3/DDR2 LogiCORE IP is provided as a full memory interface design with physical layer (PHY), highly efficient memory controller, and user interface blocks. All blocks are provided as HDL source code. Generally, the full 7 Series MIG DDR3/DDR3 design meets or exceeds customer memory design requirements. However, some applications may benefit from a custom controller that is designed specifically for the target access pattern. In these cases, Xilinx supports using the PHY only portion of the MIG 7 Series IP to interface to the custom controller. This answer record provides the necessary information to interface a custom controller to the MIG 7 Series PHY design.
02/05/2014 - Updated PDF attachment
02/12/2013 - Updated PDF attachment
11/12/2012 - Updated PDF attachment
09/11/2012 - Initial release
|Name||File Size||File Type|
|Xilinx Answer Record 51204 - MIG 7 Series DDR2/DDR3 PHY Only Designs||645 KB|