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PlanAhead - How can I change PlanAhead HDL target language from Verilog to VHDL or vice-versa?
How can I change the target language (VHDL to Verilogor vice-versa) for a PlanAhead project?
There are two ways to do this.
1. While creating a new project in theAdd Sources window, you can change the Target Language as shown below:
2. In Project Settings, change the Target Language, as shown below:
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