2. Support
  3. AR# 5121: M1.5i/2.1i Timing - What is a Timing Report File (.twr), and what does it contain?
  4. AR# 51211: PlanAhead - How can I change PlanAhead HDL target language from Verilog to VHDL or vice-versa?

AR# 51211

PlanAhead - How can I change PlanAhead HDL target language from Verilog to VHDL or vice-versa?

Description

How can I change the target language (VHDL to Verilogor vice-versa) for a PlanAhead project?

Solution

There are two ways to do this.

1. While creating a new project in theAdd Sources window, you can change the Target Language as shown below:

ar_PA.png

2. In Project Settings, change the Target Language, as shown below:

ar_PA2.png

AR# 51211
Date 12/10/2012
Status Archive
Type General Article
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