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  3. AR# 5121: M1.5i/2.1i Timing - What is a Timing Report File (.twr), and what does it contain?
  4. AR# 51216: MIG Virtex-6 v3.8 DDR3 - Why do I see 'x' on A12 address line when my test bench is not driving this?

AR# 51216

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MIG Virtex-6 v3.8 DDR3 - Why do I see 'x' on A12 address line when my test bench is not driving this?

Description

When simulating the MIG Virtex-6 DDR3 design using my own test bench, I see Address Bit A12 as 'X' even though I am not driving this bit in my test bench.

I do not see this problem when using the MIG test bench, only when using my own.

What can cause this?

Solution

ddr3_addr[12] is not driven by the user but by MIG and is used for burst chop mode, which is enabled through a mode register during initialization. 

A[12] determines (on the fly) whether or not burst chop is used during a READ and WRITE. 

If A[12] is not being driven, make sure the following parameter is set properly in the test bench:

constant C0_BURST_MODE    : string := "8";

When C0_BURST_MODE is not set correctly in the user test bench, 'X' will be seen for ddr3_addr[12] in simulation. 

AR# 51216
Date 09/12/2014
Status Active
Type General Article
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