You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
F1.5i Simulator, Virtex: Cannot simulate CLKDLL component in a Timing Simulation.
Keywords: 1.5i, Foundation, Simulator, functional, logic, clkdll, virtex
Simulating CLKDLL in Foundation Simulator 1.5i does not produce any
clock frequency, just a constant value.
This problem has been corrected for all outputs of the CLKDLL except
the DIVIDE output. This will be resolved in a future software release.
F1.5i Service Pack 2 fixes the other outputs and is available at:
Note: This software update only enable timing simulation of the CLKDLL.
Functional simulation will not work.
Was this Answer Record helpful?