2. Support
  3. AR# 5129: LogiCORE PCI32: What is the advantage of using the BAR_x_WR/RD signals as refered to in the User Guide?
  4. AR# 51296: Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases

AR# 51296

Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases

Description

ISE 14.2 and Vivado 2012.2 design tools include NEW package flight times for all Kintex-7 and Virtex-7 device/package combinations. Package flight times are typically used in the matching of trace delays for Memory Interfaces and other high speed source synchronous interfaces.

NOTE: No packages have physically changed, but flight time (i.e., package trace delay) data is now more accurate due to an improved data extraction flow.

Solution

Action Required for New 7 Series Board Designs

  • Customers must use the new flight time data in the ISE 14.2 and Vivado 2012.2 design tools.

Action Required for Existing 7 Series Board Designs

  • Use the following table based on memory data rate and check if your device/package combination is listed:

Up to 1066 Mbps

1067 to 1333 Mbps

1334 to 1866 Mbps

No Packages Affected

K325T FFG676

K410T FFG900

VX485T FFG1158

VX485T FFG1927

VX485T FFG1930

VX690T FFG1761

VX690T FFG1927

V2000T FLG1925

V2000T FHG1761

K325T FFG676

K325T FFG900

K410T FFG676

K410T FFG900

VX485T FFG1157

VX485T FFG1158

VX485T FFG1761

VX485T FFG1927

VX485T FFG1930

VX690T FFG1761

VX690T FFG1927

V2000T FLG1925

V2000T FHG1761

No Action Required

Contact Factory:

File a WebCase using the template below.

Contact Factory:

File a WebCase using the template below.

If your device/package combination is listed,follow these steps:

    1. First,download and fill in the Customer Information Template attached to this Design Advisory ("Package_Flight_Time_WebCase_Submission.xlsx").
    2. Then, create a new WebCase and attach the filled in template to it.

Xilinx Technical Support will analyze the details provided in the Customer Information Template to determine if any corrective actions are necessary for the design.

Attachments

Associated Attachments

Name File Size File Type
Package_Flight_Time_WebCase_Submission.xlsx 21 KB XLSX

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33566 Design Advisory Master Answer Record for Programmable Logic Based External Memory Interface Solutions for Virtex-6, Spartan-6, all 7 Series Devices, and all UltraScale based Devices N/A N/A
42944 Design Advisory Master Answer Record for Virtex-7 FPGA N/A N/A
46132 MIG 7 Series DDR3/DDR2 - Trace Matching and Derating Guidelines N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42944 Design Advisory Master Answer Record for Virtex-7 FPGA N/A N/A
42946 Design Advisory Master Answer Record for Kintex-7 FPGA N/A N/A
AR# 51296
Date 03/02/2013
Status Active
Type Design Advisory
Devices
Tools
IP