If targeting Zynq devices in the ISE design tools, only the "Balanced" design goal can be selected in "Design Goals & Strategies".
What is the problem?
The same design goal strategies that are used for Virtex-7 FPGA projects should be available for Zynq device projects as well. However, in ISE Design Suite 14.2, these strategies were not correctly linked for Zynq projects.
The Balanced strategy is available because it is the default setting for every family.
The design goals for Zynq devices will be added in ISE Design Suite 14.3.
To use the Virtex-7 FPGA design goal strategies for Zynq projects in ISE Design Suite 14.2, perform the following:
<DeviceList devices="virtex7,virtex7l" />
<DeviceList devices="zynq" />
Note: The /ISE/virtex7/data/*.xds files will need to be made writeable before using this procedure.