Description

Solution

1. GTP Transceiver Attribute Updates for Initial/General Engineering Sample (ES) Silicon

This table shows the GTP attribute updates required for reliable operation of the Initial/General ES silicon. When using v2.4 or earlier of the 7 Series FPGAs Transceivers Wizard, some of these attribute updates may need to be made manually to the GTP wrapper generated by the wizard. When using v2.5 of the wizard in ISE 14.5, the attributes are generated natively (except RX_OS_CFG and RXLPM_OSINT_CFG) by the wizard. When using v2.5 of the wizard in Vivado 2013.1, the exceptions are BIAS_CFG, PMA_RSV2, RXCDR_CFG, RX_OS_CFG and RXLPM_OSINT_CFG and these need to be set manually in the wrapper generated by the wizard. The updated RX reset sequence covered in (Xilinx Answer 53561) and the TX sync controller change covered in (Xilinx Answer 55009) are included in v2.5 of the wizard.

Notes:

1. Should be set to 27'h01F024C for PCI-Express Gen 1 and Gen 2.
2. For RXLPM_INCM_CFG and RXLPM_IPCM_CFG settings, refer to the RX termination use modes section below.
3. Programmable, set to 800 mV. Applies when RX_CM_SEL = 2'b11.
4. The port RXCDRLOCK is not supported. It is recommended to verify the incoming data.
5. The RXCDR_CFG settings are preliminary and under characterization. The updated settings will be added when available.
6. This setting is to support SATA requirement for REFCLK PPM with SSC: +/- 700PPM with 33KHz FM Triangular modulation of -5000PPM.

2. Use Modes/Issues

2.1. RX Termination Use Modes

For the different GTP RX termination use modes, see (Xilinx Answer 51448).

2.2. Buffer Bypass Mode

For the latest buffer bypass attributes, see (Xilinx Answer 47492).

2.3. OOB Use Mode

OOB circuitry is only used for applications such as PCI Express, SATA/SAS, etc. For designs not using OOB, PCS_RSVD_ATTR[8] is set to 1'b0; RXELECIDLEMODE[1:0] must be set to 2'b11 and RXBUF_RESET_ON_EIDLE must be set to FALSE.

2.4. RX Reset Sequence

For the RX reset sequence requirement for Production Silicon, please refer to (Xilinx Answer 53561). This updated sequence is required for production silicon but can also be used on ES silicon. When using v2.5 of the 7 Series FPGAs Transceivers Wizard, this reset sequence is included automatically.  

2.5. GTPE2_COMMON/BIAS_CFG Use Mode

Clock Forwarding Use Mode:

• The reference clock is forwarded from one Quad (essentially just the IBUFDS_GTE2 is used and this Quad is not being used otherwise in the design) to another Quad
• GTP transceiver running at -2 and -3 line rates
• Voltage swing of the reference clock is less than 400 mV (differential peak-to-peak)

Linked Answer Records

Master Answer Records