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  3. AR# 51381: 7 Series Integrated Block for PCI Express v1.4 - UCF in the example design has a TIG constraint for 125 MHz clock even for Gen1 mode

AR# 51381

7 Series Integrated Block for PCI Express v1.4 - UCF in the example design has a TIG constraint for 125 MHz clock even for Gen1 mode

Description

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

When generating 7 Series Integrated Block for PCI Express v1.4 core in Gen1 mode, the generated constraints file has a TIG constraint for 125 MHz clock as shown below:

NET "ext_clk.pipe_clock_i/clk_125mhz" TIG;

Solution

This is a known issue and will be fixed in a future release of the core. For Gen1 configuration, TIG should be removed.

Revision History
09/06/2012 - Initial Release

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 51381
Date 08/26/2013
Status Active
Type General Article
IP
  • PCI-Express (PCIe)
  • 7 Series Integrated Block for PCI Express (PCIe)
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