Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
When generating 7 Series Integrated Block for PCI Express v1.4 core in Gen1 mode, the generated constraints file has a TIG constraint for 125 MHz clock as shown below:
NET "ext_clk.pipe_clock_i/clk_125mhz" TIG;
This is a known issue and will be fixed in a future release of the core. For Gen1 configuration, TIG should be removed.
09/06/2012 - Initial Release
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.