UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51400

Vivado SysGen - "FIR Compiler v6.3 warning: block does not have a parameter named 'structural_sim'"

Description

If I open up my Vivado SysGen design, the following warning appears in the MATLAB console:

"Warning: In instantiating linked block 'fircv63_paths_four/FIR Compiler 6.3 ' : Xilinx FIR Compiler 6.3 Block block (mask) does not have a parameter named 'structural_sim'"

What does this warning mean and how do I avoid it?

Solution

This is a known issue in the System Generator 14.1, 14.2, 2012.1, and 2012.2 releases.

This warning message is harmless and is the result of a change to the simulation model for the FIR Compiler.

This warning can be resolved by saving the design file again using System Generator 2012.3 or newer release.

AR# 51400
Date Created 08/22/2012
Last Updated 06/21/2013
Status Active
Type General Article
Tools
  • System Generator for DSP - 14
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • More
  • Vivado Design Suite
  • Vivado Design Suite - 2012.1
  • Vivado Design Suite - 2012.2
  • Less
IP
  • FIR Compiler