I am trying to run the TRD in ISE GUI mode with slight modifications. I am experiencing someproblems while doing so. Isuspect that the problems I am experiencing are due to thethat fact that unlike using the batch file, I am not passing the parameters of the design being a x4, gen 2 design, and I do not know how the ISE toolis resolving this.
How can I ensure that my design is being built as a 4-lane, gen2 PCIe design?
You can pass the parameters gen2 and PCIEx4 in Synthesis propertiesas follows.
Go to Synthesis-> Process Properties -> Synthesis Options -> -define. Set define to PCIEx4, GEN2_CAP as shown in the below snapshot: