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AR# 51418

Vivado - Running pre Tcl script modifying HDL sources for Synthesis shows Synthesis out-of-date when it is actually complete


I have a Tcl script that touches my HDL source files (e.g., appends a comment in the file VHDL source files with the current date, time, version and build number).

I run this script automatically prior to running the Vivado Synthesis tool, using the pre Tcl option in the Synthesis settings.

The script runs correctly and synthesis completes. However, the synthesis status in the Vivado GUI is shown as "Out of Date" even though synthesis completed successfully. This prohibits running the implementation without manual intervention to force the Synthesis to complete status.

Why is the status being set to "Out of Date"? Can I run my script using the pre synthesis Tcl option and still avoid this issue?


The Vivado tcl.pre/tcl.post commands are designed to wrap the specific Tcl command as closely as possible. Consequently, the check for status is based on the state of the HDL source files at the beginning of the entire synthesis operation (including tcl.pre and tcl.post script commands). The status of the command is set to "Out of Date" because the source files are changed after the start of the command.

For now, the options available to the customer are all manual.

  • From the Tcl Console, after Synthesis has completed, run the following: set_property needs_refresh false [get_runs synth_1]
  • From the Tcl Console, run a Tcl script containing the above command.
  • By clicking the "more info" link on the top right corner next to the string "Synthesis and Implementation Out-of-Date", another small window opens where you can select "Force up-to-date".

Note: A post Tcl script will not work in the Synthesis Settings as this is all considered to be part of the Synthesis Step, so it cannot update the step; it is part of itself.

AR# 51418
Date 11/12/2012
Status Active
Type General Article
  • Vivado - 2012.1
  • Vivado - 2012.2