I have a Tcl script that interacts with my HDL source files (for example, it appends a comment in the file VHDL source files with the current date, time, version and build number).
I run this script automatically prior to running the Vivado Synthesis tool, using the pre Tcl option in the Synthesis settings.
The script runs correctly and synthesis completes. However, the synthesis status in the Vivado GUI is shown as "Out of Date" even though synthesis completed successfully.
This prevents me from running the implementation without manual intervention to force the Synthesis to complete status.
Why is the status being set to "Out of Date"? Can I run my script using the pre synthesis Tcl option and still avoid this issue?
The Vivado tcl.pre/tcl.post commands are designed to wrap the specific Tcl command as closely as possible.
Consequently, the check for status is based on the state of the HDL source files at the beginning of the entire synthesis operation (including tcl.pre and tcl.post script commands).
The status of the command is set to "Out of Date" because the source files are changed after the start of the command.
For now, the following options are available, but are all manual:
Note: A post Tcl script will not work in the Synthesis Settings as this is all considered to be part of the Synthesis Step, so it cannot update the step; it is part of itself.