AR# 51451


Ten Gigabit Ethernet PCS/PMA (10GBASE-KR) v2.4, 7 Series - Transmit bit errors might be seen out of reset


This issue has ben found in the Ten Gigabit Ethernet PCS/PMA core v2.4.

Depending on the relative clock delays between clk156 and clk322, the txsequence vector count output to the GT can sometimes get reset too soon resulting in incorrect data being transferred to the GT.

This results in bit errors on the link partner RX side.


This logic has been updated in the v2.4 rev3 update (attached at the end of this answer record).

The attached rev3 update also includes the rev2 updates which resolved:

  • Issues seen in hardware on cable unplug or reset resulting in failure to establish a link or FCS errors at the MAC level; see (Xilinx Answer 51282).
  • BASE-KR Training not completing after reset; see (Xilinx Answer 51312).

The attached rev3 update also includes the rev1 updates which resolved:

  • Improved hot-plug capabilities.
  • Separation of the tx and rx resets in the example design and block level.
  • Updates to improve timing closure in the Vivado tool; see (Xilinx Answer 50809).
  • Connection of signal_detect port to core FSMs.

The v2.4 rev3 core is preproduction and hardware testing continues.

To install the patch, follow the instructions in the included readme file.


Associated Attachments

Name File Size File Type 1 MB ZIP
AR# 51451
Date 09/08/2014
Status Active
Type General Article
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