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Zynq - 7000 : QoS-301 Outstanding Transaction Arbitration for ARM Cores
Can core0 be configured to allow X number of transactions on the bus and core1 be configured to allow Y number of transactions on the bus where X != Y?
The Cortex A9 core0 and core1 cannot be reconfigured.
(Zynq 7000 Technical Reference Manual), certain sources do have Advanced QoS registers that allow changes to the maximum number of outstanding transactions.
|Control boot secure settings for the slave ports of the slave interconnect.|
aw_p, aw_b, aw_r,
ar_p, ar_b, ar_r
|Control advanced QoS features, maximum number of outstanding transactions, AW and AR channel peak rates, burstiness, average rates.|
However, the only sources that have Advanced QoS registers are the AHB Masters, DMA Controller, and the L2 Cache.
The CPU is not included as something that is reconfigurable via the QoS registers.
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