AR# 51521

Zynq - 7000 : QoS-301 Outstanding Transaction Arbitration for ARM Cores

Description

Can core0 be configured to allow X number of transactions on the bus and core1 be configured to allow Y number of transactions on the bus where X != Y?

Solution

The Cortex A9 core0 and core1 cannot be reconfigured.

Per UG585 (Zynq 7000 Technical Reference Manual), certain sources do have Advanced QoS registers that allow changes to the maximum number of outstanding transactions.

Function	Name	Overview
TrustZone	security_fssw_s0 security_fssw_s1	Control boot secure settings for the slave ports of the slave interconnect.
Advanced QoS	qos_cntl, max_ot, max_comb_ot, aw_p, aw_b, aw_r, ar_p, ar_b, ar_r	Control advanced QoS features, maximum number of outstanding transactions, AW and AR channel peak rates, burstiness, average rates.

Function

Name

Overview

TrustZone

security_fssw_s0

security_fssw_s1

Control boot secure settings for the slave ports of the slave interconnect.

Advanced QoS

qos_cntl,

max_ot, max_comb_ot,

aw_p, aw_b, aw_r,

ar_p, ar_b, ar_r

Control advanced QoS features, maximum number of outstanding transactions, AW and AR channel peak rates, burstiness, average rates.

However, the only sources that have Advanced QoS registers are the AHB Masters, DMA Controller, and the L2 Cache.

The CPU is not included as something that is reconfigurable via the QoS registers.

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AR# 51521
Date	10/03/2014
Status	Active
Type	General Article
Devices	Zynq-7000
Tools	EDK ISE PlanAhead Vivado Design Suite

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AR# 51521

Zynq - 7000 : QoS-301 Outstanding Transaction Arbitration for ARM Cores

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