2. Support
  3. AR# 5154: FPGA Configuration - Is it possible to stop CCLK during configuration?
  4. AR# 51543: Disabling specific DRC checks in Vivado

AR# 51543

Disabling specific DRC checks in Vivado

Description

It is possible to set a property to disable individual DRC checks using the rule name.

Solution

Yes, this is possible.

For example, the CSCL-1 rule can be disabled with the following property setting:
set_property IS_ENABLED 0 [get_drc_checks {CSCL-1}]
AR# 51543
Date 01/20/2015
Status Active
Type General Article
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