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Design Advisory Master Answer Record for LogiCORE IP Aurora 8B10B and Aurora 64B66B
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
For a list of all current Release Notes and Known Issues for Aurora 8B10B IP, please refer to the IP Release Notes Guide:
Design Advisory Alerted on January 21, 2013:
||(Xilinx Answer 53304)
||Design Advisory for Aurora 8B10B v8.3 - OOB attribute settings update for 7 series GTX/GTH Transceivers and Zynq-7000 SoC Transceivers|
Design Advisory Alerted on October 28, 2013:
||(Xilinx Answer 51554)
||Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs |
Design Advisory Alerted on August 3, 2015:
||(Xilinx Answer 64793)
||Design Advisory for Aurora 8B10B v11.0 (or) earlier - Artix-7 GTP - Simplex RX core is not de-asserting MMCM Reset and as a result RXRESETDONE is not HIGH|
Design Advisory Alerted on May 9, 2016:
||(Xilinx Answer 66963)
||Design Advisory for Aurora 8B10B v11.0 Rev2 or later - Artix-7 GTP - Channel up toggles periodically for Verilog IP|
||Initial release |
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Linked Answer Records
Master Answer Records
Child Answer Records
- Aurora 8B/10B
- Aurora 64B/66B