Aurora 64B66B v8.1 and earlier versions of the IP core are sometimes unstable during initialization when a RESET/GT_RESET_IN input is applied to the IP multiple times.
This is observed when the core is targeted to the Xilinx 7-series devices.
This answer record provides recommendation to have a stable Aurora 64B66B core
All of the issues found in initialization phase with Aurora 64B66B v8.1 and earlier have been fixed in Aurora 64B66B v9.0 core.
Please refer to the change log or (Xilinx Answer 54368) for more details.
Recommendation for Aurora64B66B core targeting 7 series devices
Designs using Aurora 64B66B v8.1 and earlier that have not completed production testing are required to upgrade to Aurora 64B66B v9.0 core available in Vivado 2013.3.
Designs using Aurora 64B66B v8.1 and earlier that are in production and have passed verification do not need to take any action.
Upgrading to Aurora 64B66B v9.0:
Please refer to the Migrating section in the LogiCORE IP Aurora 64B/66B V9.0 Product Guide for Vivado Design Suite:
http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v9_0/pg074-aurora-64b66b.pdf
Guidelines for designs using ISE targeting 7 series device:
Xilinx does not plan to make any updates to the Aurora 64B66B v7.3 released in ISE 14.3 that supports 7 series devices.
Xilinx recommends migrating the design to Vivado Design Suite and use Aurora 64B66B v9.0 for designs targeting 7 series devices.
Major changes in Aurora 64B66B v9.0
Backward compatibility with previous versions of Aurora 64B66B
Aurora 64B66B v9.0 is expected to be backward compatible with previous versions of the core with same configuration using 7 series devices.
For example:
Aurora 64B66B v9.0 with configuration of type x is not expected to have any issues interfacing with an already in production design that has Aurora 64B66B v8.1 with the same configuration in 7 series device.
After the 2013.3 release, Xilinx plans to validate Aurora 64B66B v9.0 with Aurora 64B66B v8.1 in 7 series devices and publish the results in this answer record.
Additionally, Xilinx plans to do interoperability test between Aurora 64B66B v9.0 targeting 7 series with Aurora 64B66B v7.3 targeting 6 series devices.
Fixes done in Aurora 64B66B v9.0
Xilinx strongly recommends upgrading to the Aurora 64B66B v9.0 core.
The list below includes some of the significant IP changes in v9.0.
Fixes done in the Reset and Initialization part of the Aurora 64B66B v9.0 core
| Symptoms | Cause | Fix Details |
|---|---|---|
| Tx data corruption |
Due to warm reset | Using stable clock to synchronize the MMCM Lock signal |
| Rx data corruption | After any reset | Reset Rx buffer after CDR lock is established |
| Hot-Plug causing soft errors | Asynchronous resets on link partners | Providing early indication of reset to remote agent in hot plug sequence |
Fixes done in Architecture part of the Aurora 64B66B v9.0 core
| Category | Cause | Fix Details |
|---|---|---|
| Architecture Change | Architecture Robustness | 32 bit Rx path for increased skew margin. Addition of CB error handling and removal of redundant logic(PPM compensation logic and per lane pointer comparisons) |
| Robustness Fix | Distributed RESET logic | Common Reset sequencing across all lanes, removes per lane reset synchronizers across recovered clock and user clock |
| Feature enablement | Polarity inversion | RTL is updated to enable polarity inversion functionality |
Please contact an FAE or I/O specialist for more details about the fixes.
Revision History
10/23/2013 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
| 42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
| AR# 51554 | |
|---|---|
| Date | 01/08/2015 |
| Status | Active |
| Type | Design Advisory |
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| IP |
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