In General, the CQ/CQ# memory read clocks can be used as a differential input but the MIG 7 Series QDRII+ design does not.MIG treats the CQ/CQ# as two single end input, whereCQ and CQ# will drive different components in different situations. Both CQ/CQ# are routed through a BUFMR and then,depending on the QDRII+ component read latency value,drive the PHASERREFCLK input of the PHASER_IN or the PHASER_OUT. The PHASER_IN provides the CLK and CLKDIV inputs for the ISERDES, and the PHASER_OUT provides the CLKB input for the ISERDES.
When a QDRII+ component has 2.0 cycle read latency, CQ will be used to sample rising edge data and CQ# for falling edge data. When QDRII+ component has 2.5 cycles read latency, CQ# will be for rising edge data and CQ for falling edge data.