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  1. Xilinx - All Programmable
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  3. AR# 51577: AXI DMA - Why are my transfers limited to a seemingly arbitrary length?

AR# 51577

AXI DMA - Why are my transfers limited to a seemingly arbitrary length?

Description

I am trying to use the AXI DMA to transfer large streaming packets of data to memory.

I have set up the core according to the recommendations of the Product Guide for the core (i.e. FIFO Depth, Burst Length, and Issuing Limit), but for transfers over a certain limit, there is no activity on the bus.

Why is this happening? How do I get around it?

Solution

Despite the name, the C_SG_LENGTH_WIDTH parameter defines the width of the LENGTH registers for both Scatter Gather AND Register Direct modes.

 

If you are in Register Direct mode and are trying to do very large transfers, the C_SG_LENGTH_WIDTH parameter default may be too small to support the length of transfers that you want to do (even if you are using a seemingly legal value for the LENGTH registers).

 

Make sure to set this parameter appropriately.

AR# 51577
Date 10/02/2014
Status Active
Type General Article
IP
  • AXI DMA Controller