When I analyze the timing paths to or from the block RAM or FIFO, the clock arrival time for either the source or destination clock is incorrect and makes the requirement extra small for the PERIOD constraint analysis. I should have a full cycle for these paths.
When is this going to be fixed?
This issue is going to be resolved in ISE Design Suite 14.3, but you must re-run implementation from NGDBuild.
The work-around is to use a FROM:TO constraint for paths going to and from the block RAM (BRAM).
A tactical patch for ISE Design Suite 14.2 is available; see the ZIP file at the end of this answer record.
| Name | File Size | File Type |
|---|---|---|
| ar51580_cr673578_timing_timegrp_cs_p28xd_14_2.zip | 10 KB | ZIP |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
| 42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
| 51456 | Design Advisory Master Answer Record for Artix-7 FPGA | N/A | N/A |
| AR# 51580 | |
|---|---|
| Date | 03/02/2013 |
| Status | Active |
| Type | Design Advisory |
| Devices | |
| Tools | |