AR# 51597

Endpoint Block Plus Wrapper for PCI Express - Master Answer Record

Description

This master answer record for the Virtex-5 Endpoint Block Plus Wrapper for PCI Express core lists all release notes, Design Advisories, Known Issues and general information answer records for different versions of the core.

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This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express

Solution

Release Notes:

(Xilinx Answer 23985) Release Notes v1.1
(Xilinx Answer 24603) Release Notes v1.2
(Xilinx Answer 25162) Release Notes v1.3
(Xilinx Answer 25493) Release Notes v1.4
(Xilinx Answer 29468) Release Notes v1.5
(Xilinx Answer 30120) Release Notes v1.6
(Xilinx Answer 30632) Release Notes v1.7
(Xilinx Answer 30980) Release Notes v1.8
(Xilinx Answer 31572) Release Notes v1.9
(Xilinx Answer 32274) Release Notes v1.10
(Xilinx Answer 32741) Release Notes v1.11
(Xilinx Answer 33278) Release Notes v1.12
(Xilinx Answer 33762) Release Notes v1.13
(Xilinx Answer 35321) Release Notes v1.14
(Xilinx Answer 42760) Release Notes v1.15

Design Advisories:

(Xilinx Answer 33580) Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record
(Xilinx Answer 34444) Design Advisory for the Endpoint Block Plus Wrapper v1.13 for PCI Express - Transmit Stall Due to Link Partner Advertisement of Data Limited Completion Credits
(Xilinx Answer 33699) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Polarity Reversal on Lane 7 Could Cause the Core Not to Train all 8 Lanes
(Xilinx Answer 33534) Design Advisory for the Endpoint Block Plus for PCI Express Wrapper v1.12 for PCI Express - Using Synplify with the Block Plus Wrapper Source Code Delivery
(Xilinx Answer 33411) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - After warm reset, TX direction stalls forever because of deassertion of trn_tdst_rdy_n
(Xilinx Answer 33709) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Improve Timing Closure
(Xilinx Answer 33710) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Extended deassertions of trn_rnp_ok_n could result in completions being blocked inside the core


Known Issues/General Information:

(Xilinx Answer 30124) Endpoint Block Plus Wrapper for PCI Express - Patch updates for Endpoint Block Plus Wrapper for PCI Express
(Xilinx Answer 31164) Endpoint Block Plus Wrapper v1.8 for PCI Express - MPS of 128 or 256 bytes causes received TLP bit errors due to Expansion ROM work-around
(Xilinx Answer 31460) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - The default TXPREEMPHASIS value is incorrect for FXT devices on page 7 of the CORE Generator Customization GUI
(Xilinx Answer 32091) Endpoint Block Plus Wrapper v1.11 for PCI Express - Downstream Port model drops completions with length 64 bytes and greater
(Xilinx Answer 32727) Endpoint Block Plus Wrapper v1.11 for PCI Express - MAP fails to complete due to predictable IP placement constraints
(Xilinx Answer 32946) Endpoint Block Plus Wrapper v1.11 for PCI Express - Syntax error in x1 board_dual.v causes simulation failures
(Xilinx Answer 33850) Endpoint Block Plus Wrapper v1.13 for PCI Express - Reading and Writing Configuration Space Registers Fails
(Xilinx Answer 34706) Endpoint Block Plus Wrapper v1.15 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits Can Eventually Stall the Transmit Interface
(Xilinx Answer 37246) Endpoint Block Plus Wrapper v1.14 for PCI Express - Possible inbound packet loss if a 8b10b error occurs while previous packet is being written into receive block RAM
(Xilinx Answer 31210) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt
(Xilinx Answer 31211) Endpoint Block Plus Wrapper v1.12 for PCI Express - Link transitioning to L0s causes BAR settings to be reset
(Xilinx Answer 31646) Endpoint Block Plus Wrapper v1.14 for PCI Express - Dual core UCF problems
(Xilinx Answer 31647) Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual core implement_dual.bat file missing
(Xilinx Answer 31843) Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall
(Xilinx Answer 31850) Endpoint Block Plus Wrapper v1.12 for PCI Express - Simulation testbench writes to incorrect address for Device Control Register
(Xilinx Answer 33400) Endpoint Block Plus Wrapper v1.12 for PCI Express - ModelSim simulation results in numerous signals trimmed from the wave dump
(Xilinx Answer 33401) Endpoint Block Plus Wrapper v1.12 for PCI Express - "ERROR:sim:159 - An internal error has occurred - when disabling TX_DIFF_BOOST
(Xilinx Answer 33410) Endpoint Block Plus Wrapper v1.12 for PCI Express - Compatibility issues with ISE Project Navigator because of PIO_EP.v file module declarations and 64-bit interface ifdef declaration
(Xilinx Answer 33421) Endpoint Block Plus Wrapper v1.11 for PCI Express - Core generated for x2 lanes, Virtex-5 FXT or TXT, will not link up
(Xilinx Answer 33937) Endpoint Block Plus Wrapper for PCI Express - The implement.sh[bat] file errors out during synthesis of the wrapper files
(Xilinx Answer 33939) Endpoint Block Plus Wrapper v1.12 and later for PCI Express - How to create an NGC file of the Block Plus Wrapper files
(Xilinx Answer 51600) Endpoint Block Plus Wrapper v1.15 for PCI Express - Example Design Simulation Fails for x8 Configuration Article
(Xilinx Answer 42368) Virtex-5 Integrated PCI Express Block Plus - Debugging Guide for Link Training Issues
(Xilinx Answer 46888) Virtex-5 Endpoint Block Plus for PCI Express - Debugging and Packet Analysis Guide with Downstream Port Model and PIO Example Design
(Xilinx Answer 47109) Virtex-5 Endpoint Block Plus for PCI Express - Value for cfg_interrupt_mmenable signal Article
(Xilinx Answer 30107) Endpoint Block Plus Wrapper for PCI Express - What output should be expected when running the PIO example simulation?
(Xilinx Answer 31376) Endpoint Block Plus Wrapper v1.8 for PCI Express - Transmit Lockup on First Completion Transmitted after Link Up
(Xilinx Answer 31419) LogiCORE Endpoint Block Plus for PCI Express - ML555 not recognized by system. What is the pinout for the ML555 board?
(Xilinx Answer 31704) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Importing a v1.8 XCO to v1.9 causes "Error:sim228 -An Invalid core configuration has been detected during Customization.
(Xilinx Answer 34183) Endpoint Block Plus Wrapper v1.13 for PCI Express - How to generate an NGC from the source files
(Xilinx Answer 29236) Endpoint Block Plus Wrapper for PCI Express - How should the user application respond to requests targeting Expansion ROM? System hangs during Boot process
(Xilinx Answer 31284) Endpoint Block Plus Wrapper v1.9 for PCI Express - Per Vector Masking Bit incorrectly set inside MSI Control Register
(Xilinx Answer 32270) Endpoint Block Plus Wrapper v1.9 for PCI Express - Using non-synchronous links with Virtex-5 FXT (GTX RocketIO) could result in data errors
(Xilinx Answer 33643) Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator
(Xilinx Answer 36783) Endpoint Block Plus Wrapper v1.14 for PCI Express - Finite completion attribute not set correctly

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34655 Virtex-6 FPGA Connectivity Kit TRD - DDR3 fails to initialize N/A N/A
34652 Virtex-6 FPGA Connectivity Kit TRD - TRD Uses Custom MIG Files N/A N/A
3465 Foundation Schematic Editor F1.x: How to print all black schematics (instead of grey scale). N/A N/A
34149 LogiCORE FIR Compiler - When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioural and post-par simulation results when targeting a Spartan-3A DSP device? N/A N/A
34146 Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after Installing 11.4.1 N/A N/A
34144 Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Incorrect MMCM VCO settings result in "ERROR:PhysDesignRules:1995 - The computed value for the VCO operating frequency..." N/A N/A
34142 Spartan-6 - What is the best way to find which I/Os are related to a specific BUFIO2 site? N/A N/A
34143 Virtex-6 FPGA GTX Transceiver Wizard - Example MMCM causes errors N/A N/A
34147 LogiCORE IP Image Pipeline - Why do I receive a licensing error for the lower level cores, even though I have a full license for the iPipe Core? N/A N/A
N/A N/A
N/A N/A
9655 CPLD XC9500XL- XC9500XL device (any density) fails to configure properly after power-up N/A N/A
9652 3.1i COREGEN - Incorrect path to XilinxCoreLIb behavioral model in .veo file for v1.0 Numerically Controlled Oscillator core N/A N/A
9610 3.1i Design Manager - Bitgen will error out if -g GSR_cycle option corresponding to "Release Set/Reset" is selected for Virtex-II N/A N/A
9639 3.1i D_IP1 CORE Generator - Older COE files will not work with Distributed Memory and RAM-based Shift Register cores N/A N/A
9649 3.x FPGA Express - FPGA Express is not properly inferring BUFGs N/A N/A
9607 ChipScope Analyzer - Error: "ILA Unit Communication Failed" N/A N/A
9663 Cable - MultiLINX Cable specs and dimensions for lead connectors and posts N/A N/A
9623 FPGA Express - Positional binding is not allowed when linking the cell '...' to the target primitive design '...' FPGA-LINK-19 N/A N/A
966 Hardware Debugger 6.0.1: Error Message: Cannot find TEMP directory N/A N/A
9636 3.1i COREGEN - Foundation ISE Symbol file not generated for Single/Dual port Block Ram cores with coefficient files. N/A N/A
9690 Virtex/-E/-II, Spartan-II - Which CLKDLL/DCM outputs can drive the feedback input of a CLKDLL/DCM? N/A N/A
9624 3.1i COREGEN - Core Generator fails to generate large cores. N/A N/A
9634 9.1i Virtex MAP - How do I disable SRL16 inference in a Virtex part? N/A N/A
9640 4.2i Foundation - The HDL Language Assistant window is empty N/A N/A
9647 *Obselete* 3.1i JTAG Programmer - Dr. Watson error encountered while trying to generate an SVF program device N/A N/A
9675 3.1i Foundation ISE - Will Foundation ISE run over a network? N/A N/A
9685 LogiCORE Reed Solomon - Can the Xilinx RS Cores implement specifications of ISS 308? N/A N/A
9658 3.1i CPLD TAEngine - Fails to expand wild cards [*] when processing timing constraints N/A N/A
9621 3.1i COREGEN - If invoked from Foundation ISE, a symbol file is not generated for FFT. N/A N/A
9645 *Obselete* 3.1i XC1800 JTAG Programmer - XC1804 remains in ISP mode after operation has finished N/A N/A
9651 3.x FPGA Express, 3.1i NGDBuild - "ERROR:NgdBuild:455 - logical net 'xxxx' has multiple drivers" N/A N/A
9606 3.1i Design Manager - Post Layout Timing Report should not be automatically generated after executing MPPR N/A N/A
9618 3.1i Design Manager - Implementing Guided MAP on Virtex designs does not work N/A N/A
9648 3.1i D_IP1 Virtex-II, CORE Generator - The output initialization for a single-port block RAM VHDL behavioral model is incorrect N/A N/A
9672 3.1i Service Pack Install - Canceling the Service Pack Install gives message "Install Completed Successfully." N/A N/A
9659 3.1i SP1 : Some applications (map, par, etc) list D.19 instead of D.20 after installing Service Pack I N/A N/A
9632 FPGA Configuration - Does Xilinx support the I2C standards for configuration? N/A N/A
9646 *Obselete* 3.1i JTAG Programmer - when "write-protect" is selected, the checksum will mismatch. N/A N/A
9656 4.1i Virtex-E MAP - "FATAL_ERROR:Ncd:basncsignal.c:249:1.15.26.1 - Could not find a bel..." N/A N/A
9603 3.1i Virtex PAR - Designs with a large number of SRL16s may see poor PAR performance. N/A N/A
9697 5.1i CORE Generator - What is the role of COE and MIF files for Virtex and Virtex-II Cores? N/A N/A
9643 3.1i COREGEN - XCC does not implement string comparisons correctly N/A N/A
9657 3.1i Virtex PAR - Warning: place 1795: The placement of the source component must be in the same CLB column as the output LVDS pair N/A N/A
9684 5.1i Timing Analyzer/Trace (TRCE) - Paths that lead to and from block RAM are being incorrectly constrained (BRAMS_PORTA) N/A N/A
9602 3.x FPGA Express - Error: "Syntax error at or near 'parameter' (file: 'path' line:#) (VE-0)" N/A N/A
9612 COREGEN - How to implement a 256 point FFT using the 1024 point FFT core N/A N/A
9617 3.1i Install (HP) - Help-->Online Docs hardcoded to invoke "/tools/Netscape/Netscape -remote" on HP N/A N/A
9627 1.0 eProduct, LogiBLOX - How do I add LogiBLOX in ViewDraw's custom menu? N/A N/A
9654 CPLD XC9500- XC9500 device (any density) fails to configure properly after power-up. N/A N/A
9671 4.1i Virtex PAR - ERROR:Place:1613 - Design object (tmp0[15]) could not be placed N/A N/A
9681 3.1i Virtex-E PAR - Use of USELOWSKEWLINES impacts runtime and QOR N/A N/A
9665 1.0 eProduct - What is the flow for simulation with VHDL Coregen and Schematic? N/A N/A
9689 3.1i Virtex-II CORE Generator - No RPM is generated for shift_ram, bit_mux, bus_mux cores after I add the D_IP1 update N/A N/A
9695 ISE Text Editor - Is the ISE Text Editor accessible from outside Project Navigator? N/A N/A
9641 3.1i SP1 - 3.1i Service Pack 1 update N/A N/A
N/A N/A
72805 Zynq UltraScale+ MPSoC PS SYSMON Clocking N/A N/A
72808 UltraScale+ GTY - Adaptation Loop Override Attributes N/A N/A
72806 2019.1 Linux: MACB + PL PCS PMA link issues on Zynq UltraScale+ MPSoC N/A N/A
72136 Zynq UltraScale+: PS GEM - reason for multiple duplicate packets in custom software driver N/A N/A
72139 2019.x Zynq UltraScale+ MPSoC: Yocto or PetaLinux return warnings when you enable libmali with the fbdev windowing system N/A N/A
72130 /libstdc++.so.6: version `CXXABI_1.3.11' not found N/A N/A
72230 UltraScale/UltraScale+ - RLDRAM3 IP - Known Issues with RLDRAM3 and SEM IP Interaction N/A N/A
72238 Zynq UltraScale+ MPSoC - Vivado Readback Verify fails when PL SYSMON is configured via APB Slave Interface N/A N/A
72237 SDAccel 2019.x - Known Issues N/A N/A
72233 Video Processing Subsystem v2.0 - PG231 - Why does the SDK project for the example design fail to generate in the 2018.3 release and later versions? N/A N/A
7223 2.1i Install: HP: No option given for network installation as with PC version N/A N/A
72379 2019.1 Zynq UltraScale+ MPSoC: LwIP Support for A53 32-bit Toolchain N/A N/A
72377 2019.x Zynq-7000, Zynq UltraScale+ MPSoC: Yocto or PetaLinux build with petalinux-image-full images hangs without reaching Linux boot login prompt N/A N/A
72376 2018.x-2019.1 Zynq UltraScale+ MPSoC: USB core reset in Linux can cause issues with USB device connected if it was previously powered in U-boot N/A N/A
72372 UltraScale GTH reads different adaptation loop codes between DMON output and IBERT N/A N/A
7237 V2.1i COREGEN, Virtex, Foundation - Invalid EDIF with shorted nets produced for Virtex Dual- and Single-Port Block memory on first iteration. N/A N/A
72987 ZYNQ UltraScale+ VCU DDR4 Controller v1.0 - VCU DDR4 Controller IP synthesis errors when running the generate output products operation in Vivado 2019.1 N/A N/A
72980 Vivado - Resolving [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1 N/A N/A
72401 2019.1 Zynq UltraScale+ MPSoC: U-boot fails to read MAC address from EEPROM on ZCU102 board N/A N/A
72409 2019.1 Zynq UltraScale+ MPSoC: Linux USB 3.0 device mode does not work N/A N/A
72400 2019.1 Zynq UltraScale+ MPSoC: Yocto XRT and ZOCL commit IDs are out of sync N/A N/A
72405 ZCU111 2019.1 BSP patch files N/A N/A
72403 Vivado System Generator for DSP and Model Composer - Accessing document links on Linux OS through the MATLAB 2019a browser can result in an error. N/A N/A
72404 Simulation Libraries failures for Vivado 2019.1 N/A N/A
7240 FPGA Express - Is it possible to infer signed arithmetic modules in VHDL or Verilog? N/A N/A
72509 2019.1 Documentation Navigator - SSL error when running Documentation Navigator in Ubuntu 18 N/A N/A
72506 2019.1 - SMPTE UHD-SDI RX Subsystem v2.0 (Rev. 3) - Patch Updates for the SMPTE UHD-SDI RX Subsystem v2.0 (Rev. 3) N/A N/A
72504 10G/25G Ethernet Subsystem - 2019.1 The value set for RX Insertion loss in the GUI is not reflected in the GT N/A N/A
72505 SMPTE UHD-SDI RX Subsystem - Why is there a missing line every 2 frames when receiving 3G-SDI (1080p60) Level B with an SMPTE UHD-SDI RX subsystem? N/A N/A
72503 2018.3 Zynq UltraScale+ MPSoC VCU - How do I improve the quality of the video when using the VCU Encoder to encode video content containing scrolling text? N/A N/A
7250 4.2i Foundation Simulator - Memory write address exceeds defined memory bounds N/A N/A
72487 Vivado 2019.1 Tactical Patch - Unable to close timing on XDNN design on VU13P device N/A N/A
72480 VCU129 - Early Boards Cannot read status from SFP28s, SFP56s and SI5348 N/A N/A
72486 2019.1 RFSoC - RF Analyzer Tutorial N/A N/A
7248 4.2i Foundation Schematic - "Warning: Multiple drivers or sourceless/loadless nets detected..." N/A N/A
72588 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Encrypt Only Boot Mode - Unauthenticated Boot and Partition Headers N/A N/A
72586 2018.x Vivado Synthesis - Incorrect Logic Generation for FSM N/A N/A
72640 Alveo Data Center Accelerator Card - Card might not return after PCI Express In-Band Hot reset on AMD EPYC Host N/A N/A
72645 UltraScale+ GTM - Instructions for migrating to Vivado 2019.1.2/2019.1.3 N/A N/A
72746 Design Advisory for UltraScale+ GTH/GTY Transceivers: GTPOWERGOOD might not assert after power-up N/A N/A
72747 DMA Subsystem for PCI Express in "AXI-Bridge" mode (Vivado 2019.1) - "NUM_READ_OUTSTANDING" and "NUM_WRITE_OUTSTANDING" parameters of M_AXI_B port reset to "2" after validate BD is executed in IP Integrator N/A N/A
72744 AXI System Cache - Fails to simulate in IES N/A N/A
72745 2019.x Vivado Simulation - Known Issues N/A N/A
AR# 51597
Date 01/28/2016
Status Active
Type General Article
IP