AR# 51610


14.2 Zynq - UART Fifo data width


The UART chapter in the manual states:

> The TxFIFO's maximum data width is eight bits.

Yet, the register list claims that the bits 15:0 of the fifo register can be used. What is real the width of the fifo register for reading and writing?


8 bits, 7:0 should be used. The TRM will be updated in a future release.

AR# 51610
Date 09/06/2012
Status Active
Type General Article
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