We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51616

Zynq-7000 Example Design - GMII Ethernet through EMIOs


The example design routes the EMIO GMII interface to FPGA I/Os to be used by an FMC card with an Ethernet PHY. An Inreviun TDS-FMCL-PoE card is used for this example. An alternate board can be the Inrevium FMCL-GLAN card. Note that the FMC pinout is different for each board.

Note: An Example Design is an answer record that providestechnical tips to test a specific functionalityon Zynq-7000.Atip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It isup to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design tofulfill his needs. Limited support is provided by Xilinx on these Example Designs.

Implementation Details
Design Type PS and PL
SW Type

Standalone with LwIP.

Linux has been tested as well. Linux would require a patch to set the PHY interface to GMII. Linux by default sets the external PHY to RGMII.

CPUs Single CPU
PS Features DDR, ETH0
PL Cores Custom GMII synchronization pcore
Boards/Tools ZC702, FMCL-PoE
Xilinx Tools Version EDK 14.2
Other details --
Address Map
Base Address Size Bus Interface
BRAM 0x41200000 4K S_AXI
Files Provided
Archived XPS project with custom pcore.
Block Diagram


The custom GMII Sync pcore provides timing synchronization between the FPGA interface and the EMIO interface; both are running GMII. Only 1000 Mbps mode is supported. There is no speed detection. The ZC702 200 MHz system clock is used to generate the 125 MHz GTX clock for the Ethernet core and the PHY on the FMC.
The custom pcore is based on the CORE Generator Ethernet GMII wrapper. A PLL is used to deskew the RX Clock.

Step by Step Instructions

1. Open the xmp file with XPS
2. Generate the bitstream
3. Export the design to SDK
4. Open SDK, create a new workspace
5. Create a new C application based on the echo server template
6. Connect the FMCL-PoE board to FMC2 of the ZC702. J12 should be populated.
7. Connect the JTAG, UART, and Ethernet cables
8. Power-on the ZC702 board
9. Run the echo server application from SDK
Expected Results

User should be able to ping the FMC card and test the echo server application.


Associated Attachments

Name File Size File Type
ZC702_Eth_EMIO_GMII_142.zip 131 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51779 Zynq-7000 AP SoC - Example Designs and Tech Tips N/A N/A
AR# 51616
Date 03/02/2013
Status Active
Type General Article
  • Zynq-7000
  • EDK - 14.2
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit