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AR# 51625

Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon

Description

This answer record contains information on attribute settings, issues, and work-arounds for Virtex-7 FPGA GTH Transceiver General Engineering Sample (ES) Silicon.

Solution

1. GTH Transceiver Attribute Updates

This table shows the attribute updates required for reliable operation of this GTH silicon.

When using ISE 14.4/Vivado 2012.4, v2.4 of the 7 Series FPGAs Transceivers Wizard should be used to generate the General ES GTH settings below. Some attributes such as RXCDR_CFG, BIAS_CFG, QPLL_CFG and QPLL_CLKOUT_CFG may still need to be set manually on the wrapper.

V2.5 of the wizard in ISE 14.5/Vivado 2013.1 generates all the attributes natively except RX_DFE_KL_CFG, QPLL_CFG, QPLL_CLKOUT_CFG and QPLL_LOCK_CFG and it also includes the updated RX reset sequence covered in (Xilinx Answer 53779) and TX sync controller change covered in (Xilinx Answer 55009).

V2.6 of the wizard in ISE 14.6/Vivado 2013.2 generates all the attributes natively except QPLL_CFG, QPLL_CLKOUT_CFG and QPLL_LOCK_CFG.

For information on different silicon revisions supported by the wizard versions, please refer to (Xilinx Answer 46048).

GTH Attributes

Attribute
Value
DFE LPM
RX_CM_TRIM 4'b1010(1)
BIAS_CFG 64'h0000040000001050
ES_EYE_SCAN_EN TRUE

ES_HORZ_OFFSET 12'h000
ADAPT_CFG0 20'h00C10
PMA_RSV2 32'h1C00000A
PMA_RSV4 15'h0008
RX_BIAS_CFG 24'h0C0010
RX_DFE_AGC_CFG1 3'h4
RX_DFE_GAIN_CFG 23'h0020C0
RX_DFE_H2_CFG 12'h000
RX_DFE_H3_CFG 12'h040
RX_DFE_H4_CFG 11'h0E0
RX_DFE_H5_CFG 11'h0E0
RX_DFE_H6_CFG 11'h020
RX_DFE_H7_CFG 11'h020
RX_DFE_KL_CFG 33'h041000310
RX_DFE_KL_LPM_KH_CFG0 2'h1
RX_DFE_KL_LPM_KL_CFG0 2'h2 2'h1
RX_DFE_KL_LPM_KL_CFG2 4'h2
RX_DFE_LPM_CFG 16'h0080
RX_DFE_ST_CFG 54'h00_E100_000C_003F
RX_DFE_UT_CFG 17'h03800

RX_DFE_VP_CFG 17'h3AA3
RX_OS_CFG 13'h0080
RXLPM_HF_CFG 14'h0200
RXLPM_LF_CFG 18'h09000
PMA_RSV 32'h00000080
CFOK_CFG 42'h248_0004_0E80(2)
CFOK_CFG2 6'b100000

CFOK_CFG3 6'b100000
RXOSCALRESET_TIMEOUT 5'b00000
CPLL_CFG 24'h00BC07DC
RXCDR_LOCK_CFG(3) 6'b010101
PCS_RSVD_ATTR[8] 1'b0(4)

RXCDR_CFG(5) Full-rate: RXOUT_DIV=1 Half-rate: RXOUT_DIV=2 (1.6 to 6.55 Gb/s) Quarter-rate: RXOUT_DIV=4 (0.8 to 3.275 Gb/s) One-eighth rate: RXOUT_DIV=8 (0.5 to 1.6375 Gb/s)
Scrambled and 8B/10B with Pre-scrambling patterns

LPM/DFE mode:

CDR setting < +/- 200 ppm 83'h0_0020_07FE_2000_C208_001A (> 6.6 Gb/s)83'h0_0020_07FE_2000_C208_0018 (<= 6.6 Gb/s)

CDR setting < +/- 700 ppm
83'h0_0020_07FE_2000_C208_801A (> 6.6 Gb/s)83'h0_0020_07FE_2000_C208_8018 (<= 6.6 Gb/s)

CDR setting < +/- 1250 ppm
83'h0_0020_07FE_1000_C208_801A (> 6.6 Gb/s)83'h0_0020_07FE_1000_C208_8018 (<= 6.6 Gb/s)

LPM/DFE mode:

CDR setting < +/- 200 ppm 83'h0_0020_07FE_1000_C220_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm

83'h0_0020_07FE_1000_C220_8018

LPM/DFE mode:

CDR setting < +/- 200 ppm
83'h0_0020_07FE_0800_C220_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm
83'h0_0020_07FE_0800_C220_8018

LPM/DFE mode:

CDR setting < +/- 200 ppm
83'h0_0020_07FE_0400_C220_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm
83'h0_0020_07FE_0400_C220_8018

8B/10B without Pre-scramble pattern

LPM mode, <= 6.6 Gb/s:

CDR setting < +/- 200 ppm

83'h0_0020_07FE_2000_C208_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm

83'h0_0020_07FE_2000_C208_8018

LPM mode:

CDR setting < +/- 200 ppm

83'h0_0020_07FE_1000_C208_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm

83'h0_0020_07FE_1000_C208_8018

LPM mode:

CDR setting < +/- 200 ppm
83'h0_0020_07FE_0800_C208_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm
83'h0_0020_07FE_0800_C208_8018

LPM mode:

CDR setting < +/- 200 ppm
83'h0_0020_07FE_0400_C208_0018

CDR setting < +/- 700 ppm, +/- 1250 ppm
83'h0_0020_07FE_0400_C208_8018

SATA REFCLK PPM with SSC setting(6) 83'h0_0010_07FE_1000_C848_8018 83'h0_0008_07FE_0800_C8A0_8118 83'h0_0004_07FE_0800_C8A0_8118
PCIe Gen 3 CDR setting < +/- 200 ppm 83'h2_0020_0FFE_2000_C208_001A
Attribute VCO Rate = 6.6 Gb/s to 13.1 Gb/s (QPLL/CPLL) VCO Rate = 1.6 Gb/s to 6.6 Gb/s (CPLL)
RXPI_CFG1 2'b11 2'b0
RXPI_CFG2 2'b11 2'b0
RXPI_CFG3 2'b11 2'b11
RXPI_CFG4 1'b0 1'b1
RXPI_CFG5 1'b0 1'b1
RXPI_CFG6 3'b100 3'b001
Attribute QPLL Freq >= 8 GHz and <= 11.85 GHz  QPLL Freq > 11.85 and <= 13.1 GHz
QPLL_CFG 27'h04801C7 27'h0480187
QPLL_LOCK_CFG 16'h01E8(7) 16'h01E8
QPLL_CLKOUT_CFG 4'b1111 4'b1111

Notes:

  1. Programmable, set to 800 mV.
  2. For simulation speed-up, CFOK_CFG needs to be set a different value. Please see (Xilinx Answer 47318) for details.
  3. The RXCDRLOCK port is not supported. It is recommended to verify the incoming data.
  4. Default PCS_RSVD_ATTR[8] = 1'b0 means OOB powered down. OOB circuitry must be powered on (1'b1) for applications such as PCI Express, SATA/SAS. For designs not using OOB, RXELECIDLEMODE[1:0] must be set to 2'b11 and RXBUF_RESET_ON_EIDLE must be set to FALSE.
  5. The RXCDR_CFG settings are preliminary and are under characterization. The final settings will be added when available.
  6. This setting is to support SATA requirement for REFCLK PPM with SSC: +/- 700PPM with 33KHz FM Triangular modulation of -5000PPM.
  7. The revision 07/29/2013 changes are only required for frequencies in the range 11.85 to 12 GHz range. Note that in the frequency range of 8 to 11.3 GHz the value changed from 16'h05E8 to 16'h01E8 but these are equivalent for this frequency range.


GTH Ports

Port Value
ISE 13.4 default ISE 14.1 DFE LPM
RXDFEAGCHOLD 1'b0 1'b0 1'b0(1)
RXDFEAGCTRL 5'h00 5'h10
RXDFELFHOLD 1'b0
1'b0 1'b0(1)
RXLPMHFHOLD 1'b0 1'b0 1'b0(2)
RXLPMLFHOLD 1'b0 1'b0 1'b0(2)
RXDFEAGCOVRDEN 1'b1
RXDFEXYDEN 1'b0 1'b1    
RXOSINTCFG 4'b0110
RXOSINTEN 1'b1

Notes:
1. In DFE mode, the AGC and KL low frequency loops are set to adapt mode.
2. In LPM mode, the KH and KL loops are set to adapt mode.

2. Use Modes

2.1. GTHE2_COMMON/BIAS_CFG Use Model Change

General Use Mode:

BIAS_CFG is an attribute of the GTHE2_COMMON module and its value depends on the PLL driving the channel, and the correct QPLL settings are covered in the attribute table. However, for the correct BIAS_CFG to propagate through, the following use mode must be followed. Otherwise, BIAS_CFG will be set incorrectly in the software model to 64'h0000000000000000.

To use the correct BIAS_CFG value when using 7 series GTH Transceiver Wizard v2.1 or earlier, perform the following steps:

  1. Instantiate GTH2_COMMON in every Quad used in the design even if the QPLL is not used in that Quad.
  2. Define the correct value of BIAS_CFG in the wrapper or UCF.

Note: After setting BIAS_CFG as above, the minimum connections required so that the tools do not optimize the GTHE2_COMMON block away are as follows:

1. GTHE2_COMMON port GTREFCLK0 should be connected to the incoming reference clock.
2. GTHE2_COMMON port QPLLOUTCLK should be connected to GTHE2_CHANNEL port QPLLCLK (all the used channels on the quad).
3. GTHE2_COMMON port QPLLREFCLKSEL should be 3'b001.

The GTHE2_COMMON instantiations should be done in the gtwizard_v2_1.v file for Verilog or gtwizard_v2_1.vhd for VHDL (gtwizard_v2_1 is the default name that will be replaced with the name that the user gives to the design on page 1 of the v2.1 wizard). The GTHE2_COMMON instantiation can be obtained from a wizard example design that uses QPLL (sample "gt_wizard_v2_2.v" and "gt_wizard_v2_2.vhd" files are attached to show an example where two GTHE2_COMMON's are instantiated).

The GTHE2_COMMON module is automatically instantiated when using the 7 Series GTH Transceiver Wizard v2.2 or later in ISE 14.2/Vivado 2012.2 tools or later.

Clock Forwarding Use Mode:

This use mode requirement applies to any existing design when the criteria below are met or in general to any new designs with the Virtex-7 GTH transceiver. Following this use mode will ensure that the correct BIAS_CFG setting gets propagated which will result in improved TX jitter performance.

  • The reference clock is forwarded from one Quad (essentially just the IBUFDS_GTE2 is used and this Quad is not being used otherwise in the design) to another Quad
  • GTH transceiver running at -2 and -3 line rates
  • Voltage swing of the reference clock is less than 400 mV (differential peak-to-peak)

The GTHE2_COMMON module in the reference clock source Quad where IBUFDS_GTE2 is located should also be instantiated and the BIAS_CFG value mentioned in the attributes table should be used in the wrapper or UCF. This use mode is not implemented automatically when using v2.5 of the 7 Series FPGAs Transceivers Wizard.

2.2. Termination Use Modes

For the different RX termination use modes, refer to (Xilinx Answer 50146).

2.3. ACJTAG Use Mode

For details on the ACJTAG use mode, refer to (Xilinx Answer 52431).

2.4. Buffer Bypass Mode

For the latest buffer bypass attributes, refer to (Xilinx Answer 47492).

2.5. RX Reset Sequence

For the RX reset sequence requirement, please refer to (Xilinx Answer 53779). This updated sequence is required for Production silicon but can also be used on ES silicon. When using v2.5 of the 7 Series FPGAs Transceivers Wizard, this reset sequence is included automatically.

2.6. TX Sync Controller Change

Please refer to (Xilinx Answer 55009) for details about TX sync controller change for phase alignment in buffer bypass mode. This is fixed in v2.5 of the 7 Series FPGAs Transceivers Wizard.

Revision History

03/11/2014 - Corrected the RX_DFE_GAIN_CFG value from 23'h0000C0 to 23'h0020C0 in the table. Wizard is already setting it correctly  
01/20/2014 - Moved RXOSINTCFG and RXOSINTEN from the attributes table to the ports table
09/10/2013 - Corrected discrepancies in the attributes table for RX_DFE_KL_LPM_KH_CFG0, RX_DFE_AGC_CFG1, RX_DFE_GAIN_CFG values
07/29/2013 - Updated QPLL_CFG values for the frequency range between 11.85 and 12 GHz. No other frequencies are affected.
04/12/2013 - Updated GTHE2_COMMON/BIAS_CFG use mode to include clock forwarding and added RX reset sequence, TX sync controller sections
03/26/2013 - Updated RX_DFE_KL_CFG setting
03/07/2013 - Updated LPM port settings to be in adapt mode, Changed QPLL_CFG settings from "line rate" to QPLL frequency
02/14/2013 - Added RXCDR_CFG setting for PCIe Gen3, updated DFE port settings to be in adapt mode
01/10/2013 - Updated QPLL_CFG settings
01/07/2013 - Updated BIAS_CFG, QPLL_CFG settings and added QPLL_CLKOUT_CFG to the table.
12/12/2012 - Added the RXCDR_CFG setting for SATA SSC, added a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB and removed the Eye Scan item already covered in the Errata.
10/25/2012 - Added/updated RXCDR_CFG settings for scrambled/non-scrambled 8B/10B and non-8B/10B patterns.
10/16/2012 - Added ACJTAG and buffer bypass use modes. Added a reference to version 2.3 of the transceiver wizard for the attribute settings.
10/11/2012 - Upgraded to Design Advisory and updated the title to "General ES silicon"; removed the "RXOUTCLK port" errata item since it no longer applies for this silicon version
09/28/2012 - Updated RXCDR_CFG settings
09/06/2012 - Initial release

Attachments

Associated Attachments

Name File Size File Type
gtwizard_v2_2.v 25 KB V
gtwizard_v2_2.vhd 33 KB VHD

Linked Answer Records

Associated Answer Records

AR# 51625
Date Created 09/07/2012
Last Updated 04/17/2014
Status Active
Type Design Advisory
Devices
  • Virtex-7