This section of the MIG Design Assistant focuses on the JEDEC Specification as it applies to the MIG 7 Series DDR3/DDR3L/DDR2 FPGA designs. Below you will find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The MIG 7 Series DDR2/DDR3/DDR3L controller, upon reset, completes a JEDEC standard compliant initialization sequence. The simulation testbench skips the initial 200 s delay to speed up simulation times. In hardware, this requirement is observed. After initialization, the PHY logic completes the calibration process while adhering to all timing parameters and sending all required commands as defined by the JEDEC standards. Upon successfull calibration, the memory controller then ensures full JEDEC compliance.
The following links provide additional details regarding the MIG controller and various requirements of the JEDEC standards: