Description

Version Found: v1.04a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

When I generate a BSB design with AXI Bridge for PCI Express for the KC705 Rev C board, the core is not detected. 

The standalone core generated in the CORE Generator tool works without any issue.

Solution

This is a known issue to be fixed in a future release of the core.

To work around this issue, follow the steps below:

1. Add the following in the 'AXI Bridge for PCI Express' core instantiation in the MHS file.
    
   parameter C_PCIE_USE_MODE = 3.0
    
   
2. In the generated UCF file, comment out the following constraints:
   
   NET "*pcie_7x*/*gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_rate_i/*" TIG;
   NET "*pcie_7x*/*gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_rate_i/*" TIG;
   NET "*pcie_7x*/*gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset" TIG;

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