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  3. AR# 5169: 2.1i Design Manager - MPPR does not create revision directories; revisions don't appear in DM's view
  4. AR# 51699: AXI Bridge for PCI Express - PCIe core not detected in Base System Builder (BSB) Design for KC705 Rev C Board

AR# 51699

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AXI Bridge for PCI Express - PCIe core not detected in Base System Builder (BSB) Design for KC705 Rev C Board

Description

Version Found: v1.04a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

When I generate a BSB design with AXI Bridge for PCI Express for the KC705 Rev C board, the core is not detected. 

The standalone core generated in the CORE Generator tool works without any issue.

Solution

This is a known issue to be fixed in a future release of the core.

To work around this issue, follow the steps below:

  1. Add the following in the 'AXI Bridge for PCI Express' core instantiation in the MHS file.
     
    parameter C_PCIE_USE_MODE = 3.0
     
  2. In the generated UCF file, comment out the following constraints:

    NET "*pcie_7x*/*gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_rate_i/*" TIG;
    NET "*pcie_7x*/*gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_rate_i/*" TIG;
    NET "*pcie_7x*/*gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset" TIG;




Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 51699
Date 10/02/2014
Status Active
Type General Article
IP
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