This section of the MIG Design Assistant focuses on the performance of the MIG 7 Series DDR3/DDR2 designs. Please select from the below options to find information related:
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Performance
The 7 Series FPGA DC and Switching Characteristics data sheets include the maximum performance specifications for all MIG 7 Series IP. The MIG 7 Series tool include the supported frequency ranges for all memory configurations.
Efficiency
(Xilinx Answer 41169) Calculating Efficiency and Effective Bandwidth
Latency
(Xilinx Answer 45644) Memory Controller Latency
Additional Information
(Xilinx Answer 50549) Running DDR3L Parts at DDR3 Rates
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51675 | MIG 7 Series Solution Center Design Assistant - Core Functionality | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45644 | MIG 7 Series DDR2/DDR3 - Memory Controller Latency | N/A | N/A |
| 41169 | MIG 7 Series Solution Center - Design Assistant - DDR3 SDRAM - Calculating Efficiency and Effective Bandwidth | N/A | N/A |
| 50549 | MIG 7 Series DDR3L - Can a DDR3L part operate with 1.5V VDD and achieve the maximum rated 7 series performance for DDR3 as specified in the data sheet? | N/A | N/A |
| AR# 51705 | |
|---|---|
| Date | 02/28/2013 |
| Status | Active |
| Type | Solution Center |
| Devices | |
| IP | |