Multiple gated clocks exist in my design.
Without using global clock buffers, the clock skew is huge and leads to hold problems.
However I cannot afford to route them all to BUFGs due to limited resources.
With Synplify, gated clock conversion is performed so that the gate logic is put in the Flip-flops CE pin.
Is this available in XST?
In Synplify, the option "Fix Gated Clocks" extracts the enable logic from the clock path and converts gated clocks when applicable.
The software separates a clock net going through an AND, NAND, OR, or NOR gate by doing one of the following:
Here are some examples for eliminating gated clocks.
In XST, the feature is not available.
There is an option to "use_clock_enable", which is equivalent to the "syn_useenables" attribute in Synplify.
This is mostly applicable for the logic where the control of data to the FFs is given through some extra logic (combinational etc. ), and where XST would opt to either bring the control logic to dedicated clock enable pin or not.
In Vivado synthesis, a "gate_clock_conversion" option is available, which allows conversion of gated clocks.